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2024-04-26 - 23:02
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rackdslot4.osadl.org (updated Fri Apr 26, 2024 12:46:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
129891156134,9phc2sys0-21swapper/307:06:003
19362145126,8sleep10-21swapper/107:05:581
198742990,8sleep2259399cyclictest07:45:192
56498880,12rtkit-daemon0-21swapper/007:07:380
2592997971,4cyclictest25-21ksoftirqd/111:25:111
118582780,3sleep30-21swapper/311:00:093
2592997769,5cyclictest25-21ksoftirqd/110:05:111
129991710,2ptp4l401ktimersoftd/309:10:413
2592996962,4cyclictest25-21ksoftirqd/111:30:121
2592996961,5cyclictest25-21ksoftirqd/110:20:101
2592996961,5cyclictest25-21ksoftirqd/108:15:101
2592996860,4cyclictest25-21ksoftirqd/110:30:101
2592996860,4cyclictest25-21ksoftirqd/110:30:091
2592996760,4cyclictest25-21ksoftirqd/112:30:101
220526711,44sleep20-21swapper/207:09:322
2592996355,4cyclictest25-21ksoftirqd/110:55:091
129991620,1ptp4l401ktimersoftd/310:25:523
129991620,1ptp4l401ktimersoftd/309:32:003
191062610,2sleep319107-21systemctl08:55:313
2594995743,7cyclictest41-21ksoftirqd/312:20:103
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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