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2023-12-09 - 00:28
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Fri Dec 08, 2023 12:45:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2603621270,0sleep50-21swapper/509:42:125
1423621200,0sleep10-21swapper/111:14:001
2484121180,0sleep20-21swapper/209:36:472
776621100,0sleep20-21swapper/211:00:142
261112910,0sleep50-21swapper/512:24:015
70852790,0sleep10-21swapper/110:38:571
37862780,1sleep03746-21sshd11:45:000
244342780,0sleep40-21swapper/412:02:354
244342780,0sleep40-21swapper/412:02:354
180772780,1sleep0666-21dbus-daemon10:47:460
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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