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2024-09-07 - 17:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack0slot0.osadl.org (updated Sat Sep 07, 2024 12:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
896321220,4sleep0335499cyclictest10:32:000
245872850,1sleep30-21swapper/309:25:113
245872850,1sleep30-21swapper/309:25:113
258272810,1sleep00-21swapper/012:06:500
258272810,1sleep00-21swapper/012:06:500
259192760,0sleep10-21swapper/112:39:461
64462740,0sleep60-21swapper/612:14:426
305292740,0sleep40-21swapper/412:18:404
305292740,0sleep40-21swapper/412:18:404
320482730,0sleep50-21swapper/510:14:345
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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