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2026-06-09 - 01:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Mon Jun 08, 2026 12:45:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133721410,3sleep51675999cyclictest11:16:335
48042830,1sleep2311rcuc/210:29:492
90572790,0sleep60-21swapper/609:56:596
90572790,0sleep60-21swapper/609:56:596
292642790,0sleep50-21swapper/510:23:525
321242770,0sleep50-21swapper/510:19:355
207182770,1sleep30-21swapper/309:58:503
207182770,1sleep30-21swapper/309:58:503
186042770,1sleep00-21swapper/010:45:510
70052760,0sleep50-21swapper/509:28:215
45082760,0sleep50-21swapper/511:55:125
137622760,1sleep4491rcuc/411:23:134
23772740,1sleep60-21swapper/609:51:156
229872740,0sleep20-21swapper/212:31:072
199762730,1sleep7761rcuc/710:36:367
36622710,0sleep10-21swapper/111:45:221
229552700,1sleep40-21swapper/409:11:384
56692690,0sleep70-21swapper/709:56:297
56692690,0sleep70-21swapper/709:56:297
274962670,0sleep60-21swapper/609:12:216
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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