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2024-04-24 - 09:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Wed Apr 24, 2024 00:45:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2008221490,2sleep3722699cyclictest22:44:373
2008221490,2sleep3722699cyclictest22:44:373
95621270,0sleep00-21swapper/023:25:050
2655821090,0sleep40-21swapper/421:42:504
1787821050,0sleep00-21swapper/022:48:500
3204621010,0sleep732040-21sshd22:12:037
49012870,1sleep24903-21sshd00:26:562
302312850,0sleep70-21swapper/700:15:237
237302830,1sleep2321ktimersoftd/221:55:542
163612830,0sleep10-21swapper/123:12:561
72162820,0sleep4501ktimersoftd/400:05:094
307162820,0sleep10-21swapper/122:09:481
175932820,0sleep50-21swapper/500:21:065
153902810,0sleep60-21swapper/622:33:096
153902810,0sleep60-21swapper/622:33:096
189222800,1sleep5581rcuc/522:35:335
189222800,1sleep5581rcuc/522:35:335
156622800,0sleep50-21swapper/521:30:585
144612790,0sleep10-21swapper/121:37:341
137162780,1sleep40-21swapper/423:56:444
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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