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2019-07-16 - 02:12

Intel(R) Xeon(R) CPU E3-1265L V2 @ 2.50GHz, Linux 4.14.28-rt23 (Profile)

Latency plot of system in rack #0, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 --smi -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Sun Jul 14, 2019 12:45:13)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
715621470,0sleep70-21swapper/712:12:387
1738021420,0sleep40-21swapper/410:08:124
2342121240,0sleep60-21swapper/611:17:076
2342121240,0sleep60-21swapper/611:17:066
1864421150,0sleep40-21swapper/411:20:494
1864421150,0sleep40-21swapper/411:20:484
280821140,1sleep3411ktimersoftd/312:10:173
22522890,1sleep50-21swapper/512:08:195
232502860,1sleep123252-21kworker/u16:009:24:181
246742850,1sleep1231ktimersoftd/110:42:561
237412830,1sleep30-21swapper/309:32:203
314012820,4sleep61047399cyclictest12:30:156
301512820,0sleep60-21swapper/610:15:036
318672810,0sleep20-21swapper/211:43:552
195452810,2sleep00-21swapper/009:26:010
151832810,0sleep60-21swapper/612:13:096
109702810,0sleep30-21swapper/312:39:093
254312780,0sleep6681ktimersoftd/612:30:006
126542780,0sleep70-21swapper/709:10:217
155282770,1sleep715527-21sshd09:55:567
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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