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2024-04-23 - 21:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Tue Apr 23, 2024 12:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
751621360,0sleep20-21swapper/209:36:312
688721210,4sleep4261299cyclictest09:40:094
1020921170,1sleep2260099cyclictest11:14:482
78921050,3sleep50-21swapper/507:05:315
322762810,0sleep70-21swapper/710:01:047
300992780,1sleep50-21swapper/509:28:175
300992780,1sleep50-21swapper/509:28:165
160482780,0sleep00-21swapper/012:39:030
112952780,0sleep40-21swapper/411:51:064
67292770,4sleep3260799cyclictest11:39:503
82482750,0sleep30-21swapper/309:25:423
82482750,0sleep30-21swapper/309:25:423
140812750,0sleep40-21swapper/409:48:124
140812750,0sleep40-21swapper/409:48:114
180412740,0sleep30-21swapper/311:15:293
149462740,0sleep2311rcuc/209:26:292
149462740,0sleep2311rcuc/209:26:292
298862730,0sleep70-21swapper/709:39:097
267722730,0sleep10-21swapper/109:53:141
164282730,0sleep10-21swapper/110:24:471
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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