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2025-04-29 - 12:33
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Tue Apr 29, 2025 00:45:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
541521400,0sleep30-21swapper/323:29:073
2812521160,0sleep00-21swapper/000:21:370
216502810,1sleep00-21swapper/022:33:490
167892790,0sleep50-21swapper/523:47:045
62662780,1sleep30-21swapper/323:15:363
198592780,3sleep43226099cyclictest22:23:294
160332770,1sleep3411ktimersoftd/319:40:213
122542770,0sleep70-21swapper/723:26:227
89292760,0sleep70-21swapper/722:02:077
222292760,1sleep40-21swapper/423:37:254
79782740,1sleep40-21swapper/421:58:434
79782740,1sleep40-21swapper/421:58:434
218322740,0sleep60-21swapper/621:16:146
138852740,1sleep20-21swapper/222:42:572
128932740,0sleep60-21swapper/622:06:006
116592740,1sleep70-21swapper/723:53:157
84372730,1sleep10-21swapper/121:52:001
18592730,1sleep30-21swapper/323:08:393
298322720,0sleep00-21swapper/000:35:230
270432710,0sleep40-21swapper/422:47:484
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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