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2024-07-25 - 04:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Thu Jul 25, 2024 00:45:33)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2442721450,0sleep224426-21sshd21:39:502
2135121100,0sleep60-21swapper/600:18:406
289432840,0sleep71037-21runrttasks22:42:077
133032820,0sleep2311rcuc/222:25:422
286742800,0sleep10-21swapper/122:34:551
286742800,0sleep10-21swapper/122:34:551
208392740,0sleep40-21swapper/422:55:424
114682740,0sleep20-21swapper/223:13:022
305292730,0sleep10-21swapper/121:36:441
263952720,0sleep60-21swapper/620:25:096
8082710,0sleep70-21swapper/700:27:147
46642710,0sleep40-21swapper/423:15:544
267262710,1sleep6681ktimersoftd/600:04:296
227812710,0sleep00-21swapper/021:25:050
71102700,0sleep00-21swapper/000:02:150
232672700,0sleep20-21swapper/200:07:462
9932690,0sleep20-21swapper/223:15:282
212732630,1sleep4491rcuc/421:39:284
218912610,0sleep70-21swapper/723:28:397
2167726150,7sleep70-21swapper/719:09:577
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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