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2025-07-16 - 12:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot0.osadl.org (updated Wed Jul 16, 2025 00:45:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2838921560,4sleep61693299cyclictest21:18:076
2918221400,1sleep61693299cyclictest23:44:346
2872121240,1sleep322253-21gdbus22:49:093
51162870,2sleep30-21swapper/321:54:433
63402820,1sleep26347-21idleruntime-cro00:15:002
155972800,1sleep560-21ksoftirqd/521:10:215
141652780,1sleep50-21swapper/523:23:255
93222760,0sleep70-21swapper/723:03:237
306102760,1sleep30-21swapper/323:28:203
302622750,0sleep30-21swapper/322:06:533
165942750,0sleep00-21swapper/022:31:360
165942750,0sleep00-21swapper/022:31:350
244602740,1sleep1221rcuc/100:40:001
302392730,0sleep70-21swapper/722:29:497
41302720,0sleep10-21swapper/100:04:571
41302720,0sleep10-21swapper/100:04:571
325462720,0sleep30-21swapper/321:57:243
253312720,0sleep60-21swapper/619:25:186
18252720,0sleep20-21swapper/221:18:432
58452710,1sleep30-21swapper/322:10:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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