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2024-04-19 - 23:23

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot1s.osadl.org (updated Fri Apr 19, 2024 12:45:40)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2229099122121,1cyclictest0-21swapper/612:13:216
22290998683,2cyclictest0-21swapper/611:34:166
22294995655,1cyclictest0-21swapper/708:10:527
2121823716,17sleep10-21swapper/107:05:221
2192423414,17sleep30-21swapper/307:08:143
2181823413,18sleep00-21swapper/007:06:420
2179523313,17sleep40-21swapper/407:06:224
1953523312,17sleep20-21swapper/207:05:002
2200423110,18sleep50-21swapper/507:09:195
1991923110,18sleep70-21swapper/707:05:057
217282276,17sleep60-21swapper/607:05:286
2229099170,2cyclictest0-21swapper/611:39:156
2227399170,2cyclictest0-21swapper/307:15:203
2229499160,15cyclictest0-21swapper/711:00:007
2224999162,9cyclictest0-21swapper/008:51:070
2227799150,12cyclictest0-21swapper/407:23:454
2224999154,10cyclictest0-21swapper/008:17:050
22249991514,1cyclictest0-21swapper/008:10:350
22249991512,2cyclictest0-21swapper/008:06:390
2229499149,4cyclictest0-21swapper/711:56:307
2227799140,2cyclictest0-21swapper/407:19:304
2224999147,5cyclictest0-21swapper/008:20:210
2224999145,7cyclictest0-21swapper/008:28:410
2224999143,9cyclictest0-21swapper/008:39:070
2224999141,12cyclictest0-21swapper/007:18:110
2224999134,5cyclictest0-21swapper/007:50:560
2224999133,9cyclictest0-21swapper/007:36:570
2224999132,10cyclictest0-21swapper/007:49:590
22249991311,1cyclictest30554-21snmpd12:18:300
2224999131,11cyclictest0-21swapper/009:03:010
2224999130,9cyclictest0-21swapper/011:28:370
2224999130,4cyclictest0-21swapper/008:48:190
2229499125,6cyclictest29700-21cat08:25:157
2229499120,9cyclictest0-21swapper/707:29:317
2229499120,11cyclictest0-21swapper/710:41:457
22273991211,1cyclictest30554-21snmpd10:24:303
22273991211,1cyclictest30554-21snmpd09:02:143
22273991210,1cyclictest30554-21snmpd08:13:303
22260991212,0cyclictest30554-21snmpd12:20:151
2226099120,1cyclictest0-21swapper/110:05:031
2224999128,3cyclictest0-21swapper/009:34:170
2224999128,3cyclictest0-21swapper/009:34:170
2224999128,3cyclictest0-21swapper/009:25:070
2224999124,7cyclictest0-21swapper/007:27:570
2224999122,9cyclictest0-21swapper/009:06:210
2224999121,8cyclictest0-21swapper/011:25:000
2224999121,8cyclictest0-21swapper/010:50:220
2224999121,8cyclictest0-21swapper/007:40:370
22249991211,1cyclictest30554-21snmpd12:10:150
2224999121,10cyclictest0-21swapper/008:43:310
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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