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2025-07-13 - 09:59

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #1

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.

Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot1s.osadl.org (updated Sun Jul 13, 2025 00:45:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
399499133130,1cyclictest0-21swapper/321:53:273
400899129127,1cyclictest11769-21chk_conn_tcp00:23:175
4008991290,128cyclictest0-21swapper/521:50:355
401999128126,1cyclictest0-21swapper/700:37:037
4015991280,2cyclictest0-21swapper/619:11:596
400899127126,1cyclictest0-21swapper/500:39:225
400899126124,1cyclictest0-21swapper/519:48:365
4008991260,125cyclictest24154-21ssh21:29:285
399099126120,5cyclictest29-21ksoftirqd/222:07:322
401999125123,1cyclictest0-21swapper/722:08:257
401999125121,3cyclictest69-21ksoftirqd/720:45:417
4015991250,124cyclictest0-21swapper/623:37:076
400899125124,1cyclictest0-21swapper/521:22:015
400899125124,1cyclictest0-21swapper/520:42:055
398399125123,1cyclictest21-21ksoftirqd/100:16:481
3977991250,124cyclictest0-21swapper/020:41:120
4019991240,2cyclictest0-21swapper/721:51:377
400299124122,1cyclictest0-21swapper/423:43:504
399499124123,1cyclictest37-21ksoftirqd/319:39:003
398399124124,0cyclictest21-21ksoftirqd/100:39:271
397799124123,0cyclictest3-21ksoftirqd/021:27:270
4008991230,122cyclictest0-21swapper/521:34:385
400299123121,1cyclictest45-21ksoftirqd/419:47:254
399499123121,1cyclictest37-21ksoftirqd/319:55:463
399099123123,0cyclictest29-21ksoftirqd/223:48:272
401999122121,1cyclictest0-21swapper/700:15:487
401999122120,1cyclictest0-21swapper/719:30:467
400899122119,2cyclictest0-21swapper/523:51:195
398399121119,1cyclictest21-21ksoftirqd/121:50:351
398399121119,1cyclictest21-21ksoftirqd/121:29:281
401599120117,2cyclictest0-21swapper/623:48:096
401599120117,2cyclictest0-21swapper/621:22:156
400899120119,1cyclictest0-21swapper/522:02:385
400299120117,2cyclictest0-21swapper/422:44:264
399499120117,2cyclictest0-21swapper/300:04:563
398399120119,1cyclictest21-21ksoftirqd/121:57:421
401599119118,1cyclictest0-21swapper/600:00:066
400299119116,2cyclictest0-21swapper/421:27:384
398399119117,1cyclictest21-21ksoftirqd/100:23:171
400899118115,2cyclictest0-21swapper/523:44:525
400299118115,2cyclictest0-21swapper/422:38:324
399099118117,0cyclictest29-21ksoftirqd/223:28:122
400299117116,1cyclictest0-21swapper/400:15:014
3994991170,2cyclictest0-21swapper/323:56:373
401999116115,1cyclictest0-21swapper/723:57:037
401599116115,1cyclictest0-21swapper/619:22:596
399499116115,1cyclictest0-21swapper/321:46:393
399499116115,0cyclictest37-21ksoftirqd/322:11:283
399499116111,4cyclictest37-21ksoftirqd/323:38:443
398399116114,1cyclictest21-21ksoftirqd/121:34:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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