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2026-07-20 - 09:38
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Mon Jul 20, 2026 00:43:29)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
310618825848,7sleep50-21swapper/519:08:125
310625525520,30sleep70-21swapper/719:09:107
310621424937,8sleep40-21swapper/419:08:354
3106576994240,2cyclictest3314483-21kworker/u16:0+events_unbound21:30:094
3106576994037,2cyclictest3600070-21kworker/u16:1+events_unbound23:44:384
3106582993836,2cyclictest3733012-21kworker/u16:0+events_unbound23:52:545
3106582993835,2cyclictest3514494-21cat22:19:305
3106576993835,3cyclictest3758588-21kworker/u16:4+events_unbound00:38:094
3106584993735,2cyclictest3539347-21kworker/u16:2+events_unbound22:55:496
3106582993735,2cyclictest3366988-21kworker/u16:2+events_unbound21:47:135
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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