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2024-05-25 - 07:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Sat May 25, 2024 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
270152326050,6sleep70-21swapper/719:03:127
2703547995553,2cyclictest2715077-21kworker/u16:3+events_unbound19:10:035
2703547995350,2cyclictest2715077-21kworker/u16:3+events_unbound19:16:265
2703550994442,2cyclictest2599065-21kworker/u16:1+events_unbound19:18:356
2703547994439,4cyclictest3301429-21latency_hist00:06:445
2679189440,38rtkit-daemon0-21swapper/419:06:104
2703547993634,2cyclictest2647738-21kworker/u16:0+events_unbound19:22:085
270165423625,8sleep50-21swapper/519:05:025
2703543993531,3cyclictest2663207-21kworker/u16:5+flush-8:019:07:564
270160023524,8sleep60-21swapper/619:04:156
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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