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2025-06-12 - 15:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Jun 12, 2025 12:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
217187226149,8sleep60-21swapper/615:34:246
217172125722,30sleep70-21swapper/715:32:177
217184225343,7sleep50-21swapper/515:33:595
217187024836,8sleep40-21swapper/415:34:224
2172376994139,2cyclictest2453750-21kworker/u16:2+events_unbound18:21:006
217239099350,33cyclictest2402521-21latency_hist17:24:267
2172370993532,2cyclictest2453750-21kworker/u16:2+events_unbound18:41:335
2172364993331,2cyclictest2638681-21kworker/u16:3+events_unbound19:44:564
2172364993129,2cyclictest2536178-21kworker/u16:5+events_unbound18:46:244
2172364993128,2cyclictest2228316-21kworker/u16:1+events_unbound19:26:244
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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