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2024-09-12 - 08:58
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Thu Sep 12, 2024 00:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
356943225519,31sleep70-21swapper/718:56:047
356954623611,7sleep40-21swapper/418:57:374
3569980993533,2cyclictest3815981-21kworker/u16:1+flush-8:021:39:365
3569980993432,2cyclictest4166922-21kworker/u16:3+flush-8:000:04:485
3569980993431,3cyclictest3550379-21kworker/u16:1+events_unbound19:19:335
3569980993230,2cyclictest4001861-21kworker/u16:4+flush-8:022:49:365
356948223221,7sleep60-21swapper/618:56:436
3569980993129,2cyclictest4071428-21kworker/u16:0+events_unbound23:54:465
3569980993129,2cyclictest3680586-21kworker/u16:2+flush-8:020:14:165
3569980993028,2cyclictest4099024-21kworker/u16:2+flush-8:023:39:415
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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