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2025-02-11 - 03:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot2.osadl.org (updated Tue Feb 11, 2025 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
997711994947,2cyclictest1512514-21kworker/u16:1+events_unbound08:32:475
997704994541,3cyclictest1093364-21kworker/u16:4+events_unbound05:22:494
997730994239,2cyclictest1581956-21iostat09:07:447
99773099420,40cyclictest1021869-21latency_hist03:52:307
997711994239,2cyclictest948138-21kworker/u16:3+flush-8:004:17:455
997730994140,0cyclictest0-21swapper/709:02:547
997712993937,2cyclictest1227484-21kworker/u16:3+events_unbound06:07:486
997711993936,2cyclictest1155086-21kworker/u16:1+events_unbound05:12:445
99773099380,37cyclictest1548236-21latency_hist08:47:297
997704993735,2cyclictest718652-21kworker/u16:0+flush-8:004:57:254
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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