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2023-12-07 - 13:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2.osadl.org (updated Thu Dec 07, 2023 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
653925243,6sleep50-21swapper/507:03:425
671624737,6sleep40-21swapper/407:06:134
663323718,5sleep60-21swapper/607:05:036
64662373,29sleep70-21swapper/707:02:407
7031991611,4cyclictest4062018-21snmpd11:30:257
7031991611,4cyclictest4062018-21snmpd11:30:257
7030991615,1cyclictest0-21swapper/612:13:526
7031991412,1cyclictest515702-21iostat_ios11:16:507
7031991411,2cyclictest223208-21diskmemload09:25:317
7030991414,0cyclictest0-21swapper/610:33:166
703199139,3cyclictest4062018-21snmpd12:34:507
703199139,3cyclictest4062018-21snmpd12:09:327
703199139,3cyclictest4062018-21snmpd10:32:357
703199139,3cyclictest4062018-21snmpd09:50:447
703199139,3cyclictest4062018-21snmpd08:49:377
703199139,3cyclictest4062018-21snmpd07:58:307
703199138,4cyclictest459737-21cat10:51:567
703199138,4cyclictest4062018-21snmpd09:34:317
703199137,4cyclictest3552299-21systemd-journal07:39:097
7030991313,0cyclictest0-21swapper/609:47:336
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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