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2025-07-02 - 07:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2.osadl.org (updated Wed Jul 02, 2025 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
304211993331,2cyclictest462385-21kworker/u16:1+flush-8:005:56:175
304211993331,2cyclictest462385-21kworker/u16:1+flush-8:005:56:175
304211993129,2cyclictest710547-21kworker/u16:2+flush-8:006:58:065
304225992928,0cyclictest0-21swapper/708:52:167
304199992927,2cyclictest741236-21kworker/u16:0+events_unbound07:03:284
304225992825,2cyclictest812558-21ntp_states07:33:357
30422599280,26cyclictest926797-21latency_hist08:33:077
30422599280,26cyclictest885490-21latency_hist08:13:067
304214992826,2cyclictest369925-21kworker/u16:2+events_unbound04:47:496
304214992725,2cyclictest514119-21kworker/u16:0+events_unbound05:34:206
304214992725,2cyclictest462385-21kworker/u16:1+events_unbound05:13:056
304214992624,2cyclictest782071-21kworker/u16:0+events_unbound07:25:336
304214992624,2cyclictest617157-21kworker/u16:2+events_unbound06:18:066
304214992624,2cyclictest596578-21kworker/u16:3+events_unbound06:57:216
304214992624,2cyclictest514119-21kworker/u16:0+flush-8:005:57:046
304214992624,2cyclictest514119-21kworker/u16:0+flush-8:005:57:046
304214992624,2cyclictest462385-21kworker/u16:1+events_unbound05:46:386
304214992624,2cyclictest313286-21kworker/u16:5+events_unbound03:56:096
304214992624,2cyclictest313286-21kworker/u16:5+events_unbound03:51:016
304214992624,2cyclictest304571-21kworker/u16:3+events_unbound04:12:216
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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