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2024-04-26 - 00:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot2.osadl.org (updated Thu Apr 25, 2024 12:43:30)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
124448425822,31sleep70-21swapper/707:06:047
124448124617,8sleep40-21swapper/407:06:014
1245001993937,1cyclictest0-21swapper/708:03:437
1245001993635,0cyclictest0-21swapper/711:18:547
1245001993634,1cyclictest0-21swapper/712:18:577
1244994993532,2cyclictest1278022-21kworker/u16:0+flush-8:007:23:434
124465423524,7sleep60-21swapper/607:08:276
1245001993332,0cyclictest0-21swapper/711:08:587
123520323220,8sleep50-21swapper/507:03:455
1245001993028,1cyclictest0-21swapper/709:24:087
1244999992927,2cyclictest1288716-21kworker/u16:1+events_unbound07:48:576
1245001992827,0cyclictest0-21swapper/712:33:427
1245001992827,0cyclictest0-21swapper/710:53:437
1245001992826,1cyclictest0-21swapper/709:49:127
1245001992826,1cyclictest0-21swapper/708:58:437
1244994992826,2cyclictest1835102-21kworker/u16:0+events_unbound12:28:544
1245001992726,0cyclictest0-21swapper/707:49:097
1245001992725,1cyclictest0-21swapper/711:18:437
1244994992725,2cyclictest1288716-21kworker/u16:1+flush-8:007:43:434
1245001992624,1cyclictest0-21swapper/708:24:067
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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