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2023-05-31 - 13:14

x86 Intel Core i7-3770K @3500 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #0, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a4-7 -p99 -i200 -h400 -t4 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Wed May 31, 2023 12:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
345592999160,16cyclictest0-21swapper/608:39:426
345592999160,16cyclictest0-21swapper/604:54:446
3455928991615,1cyclictest2585421-21Xorg07:23:015
345592899160,16cyclictest0-21swapper/504:51:025
3455926991616,0cyclictest0-21swapper/408:43:124
345592699160,16cyclictest0-21swapper/405:24:434
345592699160,0cyclictest0-21swapper/407:49:364
3455929991515,0cyclictest0-21swapper/607:52:056
3455929991515,0cyclictest0-21swapper/606:43:126
3455929991513,1cyclictest2585421-21Xorg07:23:526
345592999150,15cyclictest0-21swapper/609:41:206
345592899150,15cyclictest0-21swapper/505:29:495
3455926991515,0cyclictest0-21swapper/409:18:594
3455926991515,0cyclictest0-21swapper/409:04:484
345592699150,0cyclictest0-21swapper/408:14:404
345593299145,8cyclictest1047-21snmpd09:29:587
3455929991414,0cyclictest0-21swapper/609:33:556
3455929991414,0cyclictest0-21swapper/605:28:196
345592999140,0cyclictest0-21swapper/605:43:276
345592899140,13cyclictest2585421-21Xorg09:05:575
3455926991414,0cyclictest2585421-21Xorg09:33:484
3455926991414,0cyclictest0-21swapper/407:10:404
345592699140,14cyclictest0-21swapper/404:52:344
3455929991313,0cyclictest0-21swapper/606:05:506
3455929991313,0cyclictest0-21swapper/604:54:066
345592999130,0cyclictest0-21swapper/606:16:246
3455928991313,0cyclictest0-21swapper/509:41:445
3455928991313,0cyclictest0-21swapper/508:16:185
345592899130,13cyclictest2585421-21Xorg07:41:465
345592899130,13cyclictest0-21swapper/505:55:315
3455926991313,0cyclictest0-21swapper/406:40:144
345592699130,0cyclictest0-21swapper/405:19:314
345593299125,6cyclictest1047-21snmpd09:39:137
3455929991212,0cyclictest0-21swapper/605:55:166
3455929991211,1cyclictest2585421-21Xorg04:28:156
3455929991211,1cyclictest2585421-21Xorg04:28:156
3455928991212,0cyclictest2585421-21Xorg04:45:085
3455928991212,0cyclictest0-21swapper/509:15:255
3455928991211,1cyclictest2585421-21Xorg05:09:015
3455928991211,1cyclictest2585421-21Xorg05:09:015
345592899120,12cyclictest0-21swapper/504:26:175
345592899120,12cyclictest0-21swapper/504:26:175
3455926991212,0cyclictest0-21swapper/406:16:454
3455926991212,0cyclictest0-21swapper/405:32:364
3455926991212,0cyclictest0-21swapper/405:04:424
3455926991212,0cyclictest0-21swapper/405:04:424
345593299115,5cyclictest1047-21snmpd09:40:587
345593299110,10cyclictest4153471-21cat09:14:327
345593299110,10cyclictest3605286-21cat05:29:347
345593299110,10cyclictest3516494-21cat04:49:397
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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