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2024-10-04 - 02:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Fri Oct 04, 2024 00:43:34)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
180983325216,30sleep70-21swapper/719:04:597
181058424837,8sleep50-21swapper/519:07:225
233789420,35rtkit-daemon0-21swapper/619:08:466
181071523827,8sleep40-21swapper/419:09:134
1811000993530,4cyclictest2046878-21latency_hist21:09:275
1810995993331,2cyclictest2124126-21kworker/u16:1+events_unbound21:46:054
1810995993328,4cyclictest2434420-21latency_hist00:29:274
1811005992513,5cyclictest0-21swapper/700:39:137
1811005992423,0cyclictest0-21swapper/721:29:427
1811002992422,2cyclictest1950575-21kworker/u16:2+flush-8:020:39:456
1811005992322,0cyclictest0-21swapper/720:54:537
1811000992214,8cyclictest0-21swapper/521:15:315
1810995992220,2cyclictest1757028-21kworker/u16:3+events_unbound19:54:534
1811005992120,0cyclictest0-21swapper/700:24:457
1811005992119,1cyclictest0-21swapper/700:09:407
1811002992119,2cyclictest1950575-21kworker/u16:2+flush-8:021:09:456
1811002992119,2cyclictest1901518-21kworker/u16:0+flush-8:020:14:446
1811002992119,2cyclictest1781746-21kworker/u16:4+events_unbound19:19:456
1811002992119,2cyclictest1757028-21kworker/u16:3+flush-8:019:49:436
1811005992019,0cyclictest0-21swapper/719:49:517
1811002992018,2cyclictest2376632-21kworker/u16:3+events_unbound23:59:406
1811002992017,3cyclictest1901518-21kworker/u16:0+flush-8:020:09:486
1811005991917,1cyclictest0-21swapper/723:24:447
1811002991917,2cyclictest2357087-21kworker/u16:2+events_unbound00:34:506
1811002991914,4cyclictest2066255-21latency_hist21:19:276
1810995991917,2cyclictest2289308-21kworker/u16:3+events_unbound23:19:524
1810995991915,3cyclictest2094281-21kworker/u16:3+flush-8:022:14:444
181100599184,6cyclictest0-21swapper/723:37:507
181100599184,6cyclictest0-21swapper/722:57:557
1811005991816,1cyclictest0-21swapper/720:29:397
1811002991816,2cyclictest2377872-21kworker/u16:5+events_unbound00:22:226
1811002991816,2cyclictest1969310-21kworker/u16:0+events_unbound22:39:506
1811000991814,3cyclictest1873170-21kworker/u16:2+events_unbound19:39:415
181100599174,6cyclictest0-21swapper/722:23:397
181100599173,6cyclictest0-21swapper/719:39:357
181100599173,5cyclictest0-21swapper/722:51:257
1811005991716,0cyclictest0-21swapper/720:14:537
1811005991716,0cyclictest0-21swapper/719:44:507
1811005991716,0cyclictest0-21swapper/700:29:577
1811002991715,2cyclictest2114384-21kworker/u16:2+events_unbound22:29:426
1811002991715,2cyclictest2094281-21kworker/u16:3+events_unbound22:14:336
1811002991715,2cyclictest1969310-21kworker/u16:0+events_unbound22:04:516
1811002991715,2cyclictest1950575-21kworker/u16:2+events_unbound21:29:406
1811002991715,2cyclictest1772156-21kworker/u16:1+events_unbound19:29:096
181100299170,16cyclictest0-21swapper/623:54:386
1811000991714,2cyclictest2094281-21kworker/u16:3+events_unbound22:09:405
1810995991714,2cyclictest2241039-21kworker/u16:2+events_unbound22:49:424
181100599166,9cyclictest0-21swapper/722:09:517
181100599162,6cyclictest0-21swapper/721:27:267
1811005991615,0cyclictest0-21swapper/723:39:547
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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