You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2021-01-23 - 06:29

Intel(R) Core(TM) i7-3770K CPU @ 3.50GHz, Linux 5.10.1-rt20 (Profile)

Latency plot of system in rack #0, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q --smi
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Sat Jan 23, 2021 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
38714432670,0sleep50-21swapper/521:57:235
38647772630,0sleep50-21swapper/521:49:145
38101932610,0sleep00-21swapper/020:34:050
39881712580,0sleep00-21swapper/000:02:520
376671625849,6sleep60-21swapper/619:07:316
39432862570,0sleep70-21swapper/723:14:147
38564072550,0sleep50-21swapper/521:40:415
39712102540,0sleep60-21swapper/623:44:086
376672525445,6sleep40-21swapper/419:07:374
38448512530,0sleep70-21swapper/721:27:227
376680824233,6sleep30-21swapper/319:08:483
186098420,36rtkit-daemon0-21swapper/119:07:001
376648523324,6sleep50-21swapper/519:04:175
376647323223,6sleep20-21swapper/219:04:062
376667422910,6sleep00-21swapper/019:06:530
376706799230,1cyclictest0-21swapper/419:48:554
376665322314,6sleep70-21swapper/719:06:367
376707999200,19cyclictest0-21swapper/720:34:097
376707599170,16cyclictest0-21swapper/619:59:076
376707099170,3cyclictest0-21swapper/520:14:585
376706799179,1cyclictest0-21swapper/422:54:074
39149382160,0sleep70-21swapper/722:44:187
376707599160,2cyclictest0-21swapper/620:04:436
376705199168,1cyclictest0-21swapper/021:49:310
376707999150,14cyclictest3878893-21ssh22:06:557
376707599150,7cyclictest0-21swapper/620:43:026
376707599150,7cyclictest0-21swapper/619:39:096
376706799150,1cyclictest0-21swapper/421:20:124
3767062991513,1cyclictest856-21snmpd00:31:143
376705899150,7cyclictest0-21swapper/223:02:272
39855212140,0sleep20-21swapper/223:59:102
39780192140,0sleep50-21swapper/523:51:365
39780192140,0sleep50-21swapper/523:51:365
38370272140,0sleep70-21swapper/721:19:057
37740162140,0sleep40-21swapper/419:19:134
37740162140,0sleep40-21swapper/419:19:134
376707999147,7cyclictest0-21swapper/700:31:267
376707999140,1cyclictest0-21swapper/720:06:257
376707599140,7cyclictest0-21swapper/600:21:506
376706799140,7cyclictest0-21swapper/419:51:224
376706299140,4cyclictest0-21swapper/321:00:233
376706299140,14cyclictest0-21swapper/321:51:393
3767058991412,1cyclictest856-21snmpd20:19:282
376705899140,14cyclictest0-21swapper/222:25:432
376705699140,7cyclictest0-21swapper/121:25:151
376705199140,1cyclictest0-21swapper/000:15:170
376705199140,14cyclictest0-21swapper/023:22:380
186098140,2rtkit-daemon0-21swapper/123:36:241
3767079991313,0cyclictest0-21swapper/721:10:007
376707999130,13cyclictest0-21swapper/721:17:157
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional