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2022-06-27 - 17:52

x86 Intel Core i7-3770K @3500 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #0, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a4-7 -p99 -i200 -h400 -t4 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2.osadl.org (updated Mon Jun 27, 2022 12:43:26)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
154889725950,6sleep40-21swapper/407:05:514
154699525647,6sleep50-21swapper/507:05:045
154909825243,6sleep60-21swapper/607:08:336
154829523828,6sleep70-21swapper/707:05:227
154948599170,17cyclictest0-21swapper/610:36:156
154948299170,16cyclictest0-21swapper/510:10:165
154948299170,16cyclictest0-21swapper/508:10:175
154948299160,15cyclictest1579346-21cpuspeed_turbos08:05:095
154948299160,15cyclictest0-21swapper/511:15:185
1549490991513,1cyclictest1010-21snmpd09:33:027
1549482991513,1cyclictest1794627-21awk12:15:225
154947999150,1cyclictest1569978-21ps07:45:194
1549490991412,1cyclictest1010-21snmpd11:41:567
1549490991412,1cyclictest1010-21snmpd11:41:567
1549482991414,0cyclictest0-21swapper/510:57:105
154948299141,13cyclictest0-21swapper/509:21:085
154948299141,13cyclictest0-21swapper/509:21:085
154948299140,14cyclictest0-21swapper/511:34:135
154948299140,14cyclictest0-21swapper/511:24:265
154947999140,14cyclictest0-21swapper/411:52:134
1549490991312,1cyclictest0-21swapper/711:45:277
1549490991311,1cyclictest1010-21snmpd10:50:017
1549490991311,1cyclictest1010-21snmpd08:36:137
1549485991313,0cyclictest0-21swapper/608:50:186
1549485991313,0cyclictest0-21swapper/608:01:076
1549485991312,1cyclictest1664452-21ssh10:01:436
1549482991313,0cyclictest0-21swapper/510:29:445
154948299130,13cyclictest0-21swapper/510:48:295
154948299130,13cyclictest0-21swapper/509:58:125
154948299130,13cyclictest0-21swapper/509:40:325
154948299130,0cyclictest0-21swapper/510:41:335
1549479991313,0cyclictest0-21swapper/411:32:214
1549479991313,0cyclictest0-21swapper/410:27:524
154947999130,13cyclictest0-21swapper/412:08:374
154947999130,13cyclictest0-21swapper/411:13:264
154947999130,13cyclictest0-21swapper/410:17:564
154947999130,13cyclictest0-21swapper/409:41:024
154947999130,13cyclictest0-21swapper/409:16:554
154949099129,2cyclictest1010-21snmpd07:36:537
1549490991212,0cyclictest0-21swapper/709:11:257
1549490991210,1cyclictest1010-21snmpd09:28:087
1549490991210,1cyclictest1010-21snmpd08:26:337
154949099120,0cyclictest0-21swapper/712:32:267
1549485991212,0cyclictest0-21swapper/611:30:206
1549485991212,0cyclictest0-21swapper/611:20:146
1549485991212,0cyclictest0-21swapper/610:34:316
1549485991212,0cyclictest0-21swapper/610:24:546
154948599120,12cyclictest0-21swapper/612:22:406
154948599120,12cyclictest0-21swapper/611:39:006
154948599120,12cyclictest0-21swapper/609:45:486
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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