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2025-06-19 - 17:30

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #2

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot2s.osadl.org (updated Tue May 27, 2025 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18260512810,0sleep60-21swapper/621:45:226
174796624736,8sleep70-21swapper/719:09:577
115198420,36rtkit-daemon0-21swapper/119:09:211
174774223827,8sleep60-21swapper/619:06:526
174636223827,7sleep50-21swapper/519:05:135
174779723626,7sleep40-21swapper/419:07:374
174794723525,7sleep00-21swapper/019:09:420
1748222993128,2cyclictest1898263-21kworker/u16:1+flush-8:000:29:580
174779623121,7sleep30-21swapper/319:07:363
1748232993027,2cyclictest1870656-21kworker/u16:2+events_unbound23:35:153
174775623020,7sleep20-21swapper/219:07:042
1748243992824,3cyclictest1756004-21latency_hist19:24:597
1748240992824,3cyclictest1064-21systemd-oomd19:30:176
1748240992723,3cyclictest1064-21systemd-oomd20:20:236
1748240992723,3cyclictest1064-21systemd-oomd20:15:226
1748232992725,2cyclictest1809782-21kworker/u16:2+flush-8:021:55:253
1748232992624,2cyclictest1883565-21kworker/u16:1+events_unbound23:55:213
1748240992523,2cyclictest1793091-21kworker/u16:4+events_unbound20:55:156
1748232992523,2cyclictest1873145-21kworker/u16:0+flush-8:000:05:203
1748232992523,2cyclictest1809782-21kworker/u16:2+flush-8:021:14:553
1748232992523,2cyclictest1785740-21kworker/u16:3+flush-8:021:00:173
1748232992422,2cyclictest1788179-21kworker/u16:2+flush-8:020:40:213
1748227992422,2cyclictest1854253-21kworker/u16:1+flush-8:022:50:002
1748227992422,2cyclictest1854253-21kworker/u16:1+flush-8:022:49:592
1748227992421,3cyclictest1793091-21kworker/u16:4+flush-8:020:59:592
1748222992420,3cyclictest1826838-21kworker/u16:0+flush-8:021:49:590
1748243992321,2cyclictest1898263-21kworker/u16:1+flush-8:000:35:257
1748243992321,2cyclictest1768625-21kworker/u16:2+events_unbound19:50:187
1748232992321,2cyclictest1890963-21kworker/u16:4+flush-8:000:00:143
1748232992321,2cyclictest1865854-21kworker/u16:0+flush-8:023:14:543
1748232992321,2cyclictest1815108-21kworker/u16:4+flush-8:021:34:553
1748232992321,2cyclictest1761290-21kworker/u16:0+flush-8:019:50:153
1748227992319,3cyclictest1760896-21latency_hist19:35:002
1748222992320,2cyclictest1880668-21kworker/u16:3+flush-8:023:44:590
1748243992219,3cyclictest1870656-21kworker/u16:2+events_unbound23:35:187
1748232992220,2cyclictest1861541-21kworker/u16:4+flush-8:023:24:553
1748224992220,2cyclictest1851756-21kworker/u16:4+flush-8:022:40:261
1748222992219,2cyclictest1812319-21kworker/u16:3+flush-8:021:40:000
1748243992119,2cyclictest1870656-21kworker/u16:2+flush-8:023:30:187
1748243992119,2cyclictest1812319-21kworker/u16:3+flush-8:021:39:557
1748240992119,2cyclictest1812319-21kworker/u16:3+events_unbound21:40:166
1748240992117,3cyclictest1819740-21cat21:34:596
1748234992113,7cyclictest0-21swapper/420:47:284
1748232992119,2cyclictest1785740-21kworker/u16:3+flush-8:020:59:563
1748232992119,2cyclictest1763733-21kworker/u16:3+flush-8:019:44:553
1748232992119,2cyclictest1750910-21kworker/u16:5+flush-8:019:25:263
1748232992118,2cyclictest1802854-21kworker/u16:1+events_unbound21:20:163
1748232992117,3cyclictest1863657-21latency_hist23:05:003
1748227992117,3cyclictest1834299-21latency_hist22:05:002
1748224992114,6cyclictest0-21swapper/121:42:511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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