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2021-10-26 - 23:03

Intel(R) Core(TM) i9-9900K CPU @ 3.60GHz, Linux 5.4.0-89-generic (Profile)

Latency plot of system in rack #0, slot #3
Note that this system runs a non-RT kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack0slot3.osadl.org (updated Mon Oct 25, 2021 00:46:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
131142363346,11sleep00-21swapper/019:08:420
110232362357,3sleep30-21swapper/319:05:169
118672350345,4sleep80-21swapper/819:05:2014
121522346340,4sleep110-21swapper/1119:05:243
130862343325,12sleep120-21swapper/1219:08:224
131412339321,12sleep40-21swapper/419:09:0210
129672338321,11sleep140-21swapper/1419:07:036
129022338321,11sleep100-21swapper/1019:06:112
128422338325,8sleep70-21swapper/719:05:3613
129272337319,12sleep130-21swapper/1319:06:305
131102336318,12sleep150-21swapper/1519:08:417
131942335317,12sleep50-21swapper/519:09:5111
130552335318,11sleep90-21swapper/919:08:0315
129762331312,11sleep60-21swapper/619:07:1112
131732330312,12sleep20-21swapper/219:09:338
130702330314,11sleep10-21swapper/119:08:101
13391997815,63cyclictest0-21swapper/621:53:5312
1339199729,43cyclictest0-21swapper/623:41:3712
1339199729,43cyclictest0-21swapper/623:41:3612
1339599719,62cyclictest28406-21grep20:40:172
1339199708,42cyclictest0-21swapper/619:59:0212
1339199674,22cyclictest0-21swapper/622:56:4912
1339199674,22cyclictest0-21swapper/622:56:4912
1339199664,42cyclictest0-21swapper/621:41:2612
1339199664,41cyclictest0-21swapper/620:20:0012
1339199652,42cyclictest0-21swapper/622:09:1112
1339599630,63cyclictest1322-21taskset22:20:002
1339199630,42cyclictest0-21swapper/623:50:3012
13395996141,20cyclictest20347-21ssh22:50:492
13395996141,20cyclictest20347-21ssh22:50:482
1339599590,17cyclictest0-21swapper/1023:56:402
1339599590,17cyclictest0-21swapper/1021:54:142
1339599590,17cyclictest0-21swapper/1020:05:272
1339599590,17cyclictest0-21swapper/1019:14:142
13391995917,42cyclictest0-21swapper/623:37:1312
13395995817,0cyclictest0-21swapper/1023:27:262
13395995817,0cyclictest0-21swapper/1023:11:292
13395995816,21cyclictest10194-21ssh00:05:342
1339599580,16cyclictest0-21swapper/1023:31:352
13391995817,41cyclictest0-21swapper/623:31:2612
13391995817,41cyclictest0-21swapper/623:17:1212
13391995816,42cyclictest0-21swapper/622:44:4612
13391995816,42cyclictest0-21swapper/622:26:5512
13391995816,42cyclictest0-21swapper/620:03:4312
13391995816,42cyclictest0-21swapper/619:54:0012
13391995816,42cyclictest0-21swapper/619:33:3612
13395995716,20cyclictest0-21swapper/1023:54:072
13395995716,20cyclictest0-21swapper/1023:45:032
13395995716,20cyclictest0-21swapper/1023:45:022
13395995716,20cyclictest0-21swapper/1000:19:132
13395995716,0cyclictest0-21swapper/1021:17:522
13391995716,41cyclictest0-21swapper/622:48:5612
13391995716,41cyclictest0-21swapper/622:37:2912
13391995716,41cyclictest0-21swapper/622:12:0612
13391995716,41cyclictest0-21swapper/621:23:4212
13391995716,41cyclictest0-21swapper/620:20:3212
13391995716,41cyclictest0-21swapper/620:14:0912
13391995716,41cyclictest0-21swapper/620:05:0412
13391995716,41cyclictest0-21swapper/619:39:5012
13391995716,41cyclictest0-21swapper/600:20:1712
13391995716,0cyclictest0-21swapper/623:23:3612
13391995715,42cyclictest0-21swapper/621:19:0212
13391995715,21cyclictest0-21swapper/619:12:0612
13395995615,41cyclictest0-21swapper/1023:24:492
13395995615,20cyclictest0-21swapper/1021:25:262
13395995615,20cyclictest0-21swapper/1020:10:382
13395995615,0cyclictest0-21swapper/1021:46:072
13395995615,0cyclictest0-21swapper/1020:03:022
13395995614,42cyclictest0-21swapper/1000:03:052
13391995615,41cyclictest0-21swapper/621:06:4612
13391995615,41cyclictest0-21swapper/620:37:5112
13391995615,41cyclictest0-21swapper/620:28:5712
13391995615,41cyclictest0-21swapper/619:15:0212
13391995615,41cyclictest0-21swapper/600:14:1712
13395995514,20cyclictest0-21swapper/1022:11:112
13395995514,0cyclictest0-21swapper/1021:10:562
13391995515,40cyclictest0-21swapper/600:26:2412
13391995514,41cyclictest0-21swapper/623:46:3112
13391995514,41cyclictest0-21swapper/623:46:3012
13391995514,41cyclictest0-21swapper/620:42:0612
13391995514,41cyclictest0-21swapper/620:34:0812
13391995514,41cyclictest0-21swapper/620:34:0812
13391995514,41cyclictest0-21swapper/619:45:2712
13391995514,41cyclictest0-21swapper/619:28:1512
13391995514,41cyclictest0-21swapper/619:21:3612
13391995513,42cyclictest0-21swapper/620:48:2412
13395995414,40cyclictest0-21swapper/1000:21:022
13395995413,41cyclictest0-21swapper/1023:01:112
13395995413,20cyclictest0-21swapper/1023:06:092
13395995413,0cyclictest0-21swapper/1022:20:542
13391995416,21cyclictest26781-21ssh21:14:2512
13391995414,40cyclictest0-21swapper/619:40:4612
13391995414,40cyclictest0-21swapper/619:40:4612
13391995413,41cyclictest0-21swapper/621:02:3312
13395995312,24cyclictest0-21swapper/1022:43:532
13395995312,20cyclictest0-21swapper/1022:03:132
13395995312,20cyclictest0-21swapper/1021:30:392
13395995312,0cyclictest0-21swapper/1021:56:572
13395995312,0cyclictest0-21swapper/1019:19:202
13395995312,0cyclictest0-21swapper/1000:27:582
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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