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2024-04-27 - 06:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot3.osadl.org (updated Sat Apr 27, 2024 00:46:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19060752368362,4sleep50-21swapper/519:08:0911
19061362365344,14sleep90-21swapper/919:09:0115
19058902360354,4sleep40-21swapper/419:05:5910
19061392356315,14sleep120-21swapper/1219:09:044
19058552354347,4sleep80-21swapper/819:05:3114
19059782350342,5sleep130-21swapper/1319:07:125
19061252345308,13sleep150-21swapper/1519:08:517
19028922344336,5sleep140-21swapper/1419:05:056
19059332343322,14sleep70-21swapper/719:06:3413
19059152343324,13sleep100-21swapper/1019:06:212
19059952342322,13sleep60-21swapper/619:07:2112
19058882342304,13sleep20-21swapper/219:05:578
19059472341317,16sleep30-21swapper/319:06:479
19050382339331,5sleep10-21swapper/119:05:241
19060822332312,13sleep110-21swapper/1119:08:153
19060122330309,14sleep00-21swapper/019:07:310
190648299415,11cyclictest0-21swapper/1423:13:206
190648299415,11cyclictest0-21swapper/1423:13:206
190648299415,11cyclictest0-21swapper/1421:34:286
190648299415,11cyclictest0-21swapper/1420:39:336
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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