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2022-05-25 - 10:04

x86 Intel Core i9-9900K @3600 MHz, Linux 5.15.2-rt19 (Profile)

Latency plot of system in rack #0, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot3.osadl.org (updated Wed May 25, 2022 00:46:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
12049972363322,14sleep130-21swapper/1319:05:295
12053412360319,13sleep80-21swapper/819:09:5814
12052372352332,13sleep150-21swapper/1519:08:287
12052842344303,14sleep70-21swapper/719:09:0813
12052452344325,13sleep50-21swapper/519:08:3311
12050582342321,14sleep140-21swapper/1419:06:186
12051962341322,13sleep100-21swapper/1019:07:502
12051342341322,7sleep120-21swapper/1219:07:054
12053242339319,14sleep90-21swapper/919:09:4215
12051892339320,13sleep30-21swapper/319:07:439
12050452339317,14sleep60-21swapper/619:06:0912
12051602338319,13sleep110-21swapper/1119:07:193
12052052337302,28sleep20-21swapper/219:07:598
12052762335313,14sleep00-21swapper/019:09:000
12033382333325,5sleep10-21swapper/119:05:161
12053172332311,14sleep40-21swapper/419:09:3610
1205621995212,20cyclictest152843-21containerd19:34:2915
1205626993817,21cyclictest0-21swapper/1419:34:306
120562199360,16cyclictest0-21swapper/919:18:0515
14062582340,0sleep100-21swapper/1022:12:342
12288362340,0sleep20-21swapper/219:35:118
13605282330,0sleep130-21swapper/1321:43:475
12822462330,0sleep150-21swapper/1520:40:017
12774402320,0sleep30-21swapper/320:35:019
120562799300,28cyclictest0-21swapper/1521:27:517
120562399305,0cyclictest0-21swapper/1122:48:563
120562399294,0cyclictest0-21swapper/1122:59:543
120562399294,0cyclictest0-21swapper/1120:26:093
120562399294,0cyclictest0-21swapper/1120:26:083
14604132270,0sleep150-21swapper/1522:47:527
13478232270,0sleep120-21swapper/1221:35:124
12276442270,0sleep70-21swapper/719:35:0113
15674852260,0sleep20-21swapper/223:56:168
15674852260,0sleep20-21swapper/223:56:158
15133392250,0sleep70-21swapper/723:21:3913
15133392250,0sleep70-21swapper/723:21:3813
120562399251,11cyclictest0-21swapper/1122:15:593
120562399250,25cyclictest0-21swapper/1120:04:113
120561799250,15cyclictest0-21swapper/522:51:5811
120561799250,15cyclictest0-21swapper/521:48:5911
120562399240,11cyclictest0-21swapper/1122:37:573
120562399240,0cyclictest0-21swapper/1119:20:153
120562399240,0cyclictest0-21swapper/1119:20:143
16020512230,0sleep40-21swapper/400:20:0410
120562399230,10cyclictest0-21swapper/1121:10:053
120562399230,10cyclictest0-21swapper/1120:48:063
120562399230,10cyclictest0-21swapper/1119:42:133
1205618992221,1cyclictest1255297-21nmbd19:34:3012
1205607992222,0cyclictest0-21swapper/220:01:478
120562599210,21cyclictest0-21swapper/1319:18:065
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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