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2023-06-02 - 21:46

x86 Intel Core i9-9900K @3600 MHz, Linux 5.15.2-rt19 (Profile)

Latency plot of system in rack #0, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot3.osadl.org (updated Fri Jun 02, 2023 12:46:00)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8180812371352,13sleep40-21swapper/407:08:0510
8180532361315,14sleep150-21swapper/1507:07:457
8179912361355,4sleep70-21swapper/707:06:4813
8181402354348,4sleep100-21swapper/1007:08:432
8180882351310,14sleep110-21swapper/1107:08:123
8181462350330,14sleep130-21swapper/1307:08:465
8179542348305,14sleep80-21swapper/807:06:1614
8181312345305,14sleep50-21swapper/507:08:3811
8179182341321,14sleep90-21swapper/907:05:4615
8180722340321,13sleep120-21swapper/1207:07:574
8181492339320,13sleep140-21swapper/1407:08:476
8179702337316,14sleep60-21swapper/607:06:3012
8179662336317,13sleep30-21swapper/307:06:289
8180392334315,13sleep10-21swapper/107:07:301
8179482332313,13sleep20-21swapper/207:06:118
8181202328309,13sleep00-21swapper/007:08:330
8184559910016,21cyclictest0-21swapper/1310:49:575
818455999713,21cyclictest0-21swapper/1309:26:185
818455999713,21cyclictest0-21swapper/1309:26:175
818455999512,20cyclictest0-21swapper/1308:41:245
818455999412,0cyclictest0-21swapper/1307:39:265
81845599917,21cyclictest0-21swapper/1312:07:095
81845599917,21cyclictest0-21swapper/1309:31:005
81845599917,21cyclictest0-21swapper/1309:30:595
81845599873,21cyclictest0-21swapper/1308:53:355
818455998410,74cyclictest1057543-21ssh10:35:165
818457998017,21cyclictest0-21swapper/1508:42:387
818455998017,21cyclictest0-21swapper/1312:22:545
818455998017,21cyclictest0-21swapper/1307:56:435
818457997917,42cyclictest0-21swapper/1511:33:307
818457997917,42cyclictest0-21swapper/1508:38:347
818457997916,42cyclictest0-21swapper/1509:32:317
818457997916,42cyclictest0-21swapper/1509:32:317
818457997916,21cyclictest0-21swapper/1511:56:537
818455997916,21cyclictest0-21swapper/1312:30:055
818457997815,21cyclictest0-21swapper/1512:34:227
818455997816,21cyclictest0-21swapper/1309:35:055
818455997816,20cyclictest0-21swapper/1310:22:155
818455997816,20cyclictest0-21swapper/1308:07:265
818455997816,20cyclictest0-21swapper/1308:07:255
818455997816,0cyclictest0-21swapper/1310:02:575
818455997816,0cyclictest0-21swapper/1309:14:185
818455997816,0cyclictest0-21swapper/1308:36:455
818455997815,21cyclictest0-21swapper/1307:28:075
818455997815,21cyclictest0-21swapper/1307:11:315
818455997815,0cyclictest0-21swapper/1308:13:255
818455997714,21cyclictest0-21swapper/1308:03:565
818455997714,21cyclictest0-21swapper/1307:48:355
818457997614,21cyclictest847165-21missed_timers07:40:237
818455997614,21cyclictest0-21swapper/1312:16:205
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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