You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2021-01-24 - 23:50

Intel(R) Core(TM) i9-9900K CPU @ 3.60GHz, Linux 5.10.1-rt20 (Profile)

Latency plot of system in rack #0, slot #3
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack0slot3.osadl.org (updated Sun Jan 24, 2021 12:45:59)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
184292362345,11sleep150-21swapper/1507:09:547
182592359353,4sleep00-21swapper/007:08:020
184022358322,11sleep90-21swapper/907:09:3215
173932356349,5sleep120-21swapper/1207:05:164
181442353336,11sleep140-21swapper/1407:06:406
147672352314,12sleep130-21swapper/1307:05:015
167172351345,4sleep60-21swapper/607:05:1012
182182349331,12sleep70-21swapper/707:07:3713
183702347329,12sleep30-21swapper/307:09:099
181592346330,10sleep100-21swapper/1007:06:522
181122346309,11sleep20-21swapper/207:06:128
184012345328,11sleep80-21swapper/807:09:3114
183742342325,11sleep50-21swapper/507:09:1111
183732335319,11sleep40-21swapper/407:09:1010
184322334317,11sleep10-21swapper/107:09:561
181772331314,11sleep110-21swapper/1107:07:093
186119912339,42cyclictest11783-21sh10:44:1412
1861199652,21cyclictest1166-21gdbus07:20:0112
1861799610,42cyclictest17028-21diskmemload10:01:134
18611995917,42cyclictest0-21swapper/612:36:4012
18611995917,42cyclictest0-21swapper/611:00:0012
18611995917,42cyclictest0-21swapper/610:37:3412
18611995917,42cyclictest0-21swapper/610:34:3012
18611995917,42cyclictest0-21swapper/610:14:3812
18611995917,42cyclictest0-21swapper/609:11:3712
18611995917,42cyclictest0-21swapper/608:41:0312
18611995917,42cyclictest0-21swapper/608:27:5312
18611995917,0cyclictest0-21swapper/609:16:4012
1861199590,17cyclictest0-21swapper/609:37:2812
18611995817,0cyclictest0-21swapper/612:03:0212
18611995817,0cyclictest0-21swapper/610:05:5012
18611995816,42cyclictest0-21swapper/612:28:3912
18611995816,42cyclictest0-21swapper/612:28:3812
18611995816,42cyclictest0-21swapper/612:13:0512
18611995816,42cyclictest0-21swapper/611:48:4012
18611995816,42cyclictest0-21swapper/611:36:3812
18611995816,42cyclictest0-21swapper/611:15:3512
18611995816,42cyclictest0-21swapper/611:09:0412
18611995816,42cyclictest0-21swapper/611:09:0412
18611995816,42cyclictest0-21swapper/610:46:4012
18611995816,42cyclictest0-21swapper/610:17:3612
18611995816,42cyclictest0-21swapper/609:51:0212
18611995816,42cyclictest0-21swapper/609:22:5512
18611995816,42cyclictest0-21swapper/608:58:2512
18611995816,42cyclictest0-21swapper/608:52:1712
18611995816,42cyclictest0-21swapper/608:47:2712
18611995816,42cyclictest0-21swapper/608:47:2712
18611995816,42cyclictest0-21swapper/608:00:2312
18611995716,41cyclictest17028-21diskmemload10:52:3012
18611995716,41cyclictest0-21swapper/611:55:3612
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional