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2026-03-06 - 09:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot3s.osadl.org (updated Fri Mar 06, 2026 00:44:45)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
29543722277214,16sleep40-21swapper/419:07:184
29543672275266,6sleep00-21swapper/019:07:140
29545472258210,17sleep70-21swapper/719:09:387
29544112258211,17sleep10-21swapper/119:07:471
29544242255233,14sleep50-21swapper/519:07:595
29544632246219,17sleep20-21swapper/219:08:282
29544552244233,7sleep30-21swapper/319:08:213
29542932244218,17sleep60-21swapper/619:06:166
2954880994134,5cyclictest3067399-21ntpq22:30:211
295487499326,24cyclictest0-21swapper/021:40:140
2954874993231,1cyclictest3057081-21kworker/0:0+events22:25:130
2954874993129,1cyclictest2985559-21kworker/0:0+events20:05:180
2954874993129,1cyclictest2985559-21kworker/0:0+events20:05:170
2954892993016,12cyclictest0-21swapper/421:15:114
2954874993023,5cyclictest0-21swapper/023:10:150
295489799280,24cyclictest0-21swapper/522:54:405
2954892992815,11cyclictest0-21swapper/421:35:194
2954892992814,12cyclictest0-21swapper/422:40:234
2954892992814,12cyclictest0-21swapper/422:40:234
2954897992726,1cyclictest0-21swapper/520:05:185
2954897992726,1cyclictest0-21swapper/520:05:175
295490699260,24cyclictest0-21swapper/722:07:337
295490699260,24cyclictest0-21swapper/721:52:457
2954888992622,3cyclictest1393-21snmpd23:16:413
2954874992622,3cyclictest1393-21snmpd20:59:070
2954906992521,3cyclictest1393-21snmpd22:25:517
295490699250,23cyclictest0-21swapper/722:49:017
295490699250,1cyclictest0-21swapper/721:27:047
2954897992518,5cyclictest0-21swapper/520:37:275
295489799251,22cyclictest0-21swapper/523:59:395
295489799250,1cyclictest0-21swapper/522:24:425
2954892992521,3cyclictest1393-21snmpd23:36:204
2954892992521,3cyclictest1393-21snmpd23:08:554
2954892992521,3cyclictest1393-21snmpd20:53:524
2954892992521,3cyclictest1393-21snmpd20:07:204
2954892992521,3cyclictest1393-21snmpd20:07:204
2954892992518,5cyclictest0-21swapper/423:45:334
2954892992518,3cyclictest0-21swapper/422:55:144
2954892992518,3cyclictest0-21swapper/420:36:214
295489299250,24cyclictest0-21swapper/400:10:244
295489299250,23cyclictest0-21swapper/421:32:324
2954888992521,3cyclictest1393-21snmpd20:54:483
2954888992521,3cyclictest1393-21snmpd20:44:093
2954888992518,5cyclictest0-21swapper/320:35:243
2954883992521,3cyclictest1393-21snmpd21:55:442
2954883992521,3cyclictest1393-21snmpd21:54:232
2954883992521,3cyclictest1393-21snmpd21:20:282
2954883992521,3cyclictest1393-21snmpd20:01:292
2954880992520,3cyclictest1393-21snmpd20:29:211
2954874992522,2cyclictest3068738-21kworker/0:1+events22:48:170
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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