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2025-07-19 - 08:04
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Note that this system runs a non-RT kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot4.osadl.org (updated Thu Jul 17, 2025 00:46:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
24134522367321,15sleep70-21swapper/719:07:5113
24132602362315,15sleep60-21swapper/619:05:4012
24134112361316,15sleep50-21swapper/519:07:1611
24135782353310,34sleep140-21swapper/1419:09:346
24135202343321,15sleep150-21swapper/1519:08:487
24134982343320,15sleep130-21swapper/1319:08:285
24132872343321,14sleep80-21swapper/819:05:5914
24132882342320,14sleep90-21swapper/919:06:0015
24135652341319,14sleep20-21swapper/219:09:238
24135062341318,15sleep30-21swapper/319:08:369
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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