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2024-04-20 - 10:29
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot4.osadl.org (updated Sat Apr 20, 2024 00:46:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
18745032345322,15sleep90-21swapper/919:07:4715
18745762344320,15sleep50-21swapper/519:08:4711
18746122342318,15sleep40-21swapper/419:09:1810
18745042342318,15sleep100-21swapper/1019:07:482
18744722342320,14sleep10-21swapper/119:07:231
18744642342316,16sleep120-21swapper/1219:07:174
18744542342318,15sleep20-21swapper/219:07:078
18744432342319,14sleep80-21swapper/819:06:5714
18744482341317,15sleep130-21swapper/1319:07:025
18746572340316,15sleep60-21swapper/619:09:5312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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