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2024-09-17 - 01:48

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot4s.osadl.org (updated Tue Sep 17, 2024 00:47:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
19129542413392,13sleep80-21swapper/819:07:1814
19129232378371,4sleep30-21swapper/319:06:579
19130332370329,14sleep150-21swapper/1519:08:147
19131242367343,15sleep120-21swapper/1219:09:324
19130082363322,15sleep50-21swapper/519:08:0411
19130982362355,4sleep60-21swapper/619:09:0912
19129732356313,13sleep100-21swapper/1019:07:372
19128592354311,13sleep00-21swapper/019:06:060
19130892352328,15sleep140-21swapper/1419:09:016
19129702352329,14sleep70-21swapper/719:07:3313
19130052346322,14sleep20-21swapper/219:08:018
19130842344321,14sleep90-21swapper/919:08:5715
19130042344319,15sleep10-21swapper/119:08:001
19130862341318,13sleep110-21swapper/1119:08:583
19131572340317,14sleep40-21swapper/419:09:5610
19127972340317,14sleep130-21swapper/1319:05:165
19135579910142,29cyclictest0-21swapper/323:04:499
1913574999234,28cyclictest0-21swapper/923:04:4815
1913552998528,29cyclictest0-21swapper/223:04:498
1913588998324,30cyclictest0-21swapper/1323:04:475
1913583998325,30cyclictest0-21swapper/1223:04:484
1913562997833,45cyclictest0-21swapper/523:04:4811
21560792580,0sleep50-21swapper/500:01:2011
1913549995352,1cyclictest34-21ksoftirqd/123:04:481
1913581994948,1cyclictest3502-21Xorg23:04:493
1913569994947,1cyclictest2120323-21kworker/u32:2+events_unbound23:36:0913
1913569994947,1cyclictest2120323-21kworker/u32:2+events_unbound23:36:0913
1913569994840,4cyclictest0-21swapper/720:05:1213
1913569994840,4cyclictest0-21swapper/720:05:1213
1913569994742,5cyclictest2072747-21kworker/u32:4+events_unbound22:44:5613
1913569994741,5cyclictest1970588-21kworker/u32:1+events_unbound20:45:2913
1913569994643,2cyclictest2125712-21kworker/u32:1+events_unbound00:13:0613
1913569994642,4cyclictest0-21swapper/723:10:3313
1913569994638,4cyclictest976890-21kworker/7:2-mm_percpu_wq21:01:0413
1913569994638,4cyclictest0-21swapper/700:31:3013
1913569994637,4cyclictest0-21swapper/720:20:0013
191356999460,1cyclictest0-21swapper/720:54:5813
1913569994541,0cyclictest0-21swapper/723:01:0513
1913569994537,4cyclictest0-21swapper/719:32:5013
191356999450,41cyclictest861rcuc/722:18:4813
1913569994440,0cyclictest2118355-21kworker/u32:0-events_unbound23:19:1513
1913569994437,3cyclictest976890-21kworker/7:2-mm_percpu_wq00:24:0013
1913569994436,4cyclictest0-21swapper/722:13:2813
1913569994436,4cyclictest0-21swapper/721:39:4413
1913569994436,4cyclictest0-21swapper/720:02:0013
1913569994436,4cyclictest0-21swapper/720:02:0013
1913569994436,4cyclictest0-21swapper/700:27:3613
1913569994435,4cyclictest0-21swapper/719:45:3613
1913569994431,4cyclictest0-21swapper/723:27:0713
1913569994431,4cyclictest0-21swapper/723:27:0713
1913569994429,11cyclictest0-21swapper/722:50:0813
191356999440,40cyclictest0-21swapper/722:39:0413
1913569994340,3cyclictest0-21swapper/721:08:5013
1913569994339,4cyclictest0-21swapper/723:40:0013
1913569994339,4cyclictest0-21swapper/720:39:2913
1913569994336,3cyclictest0-21swapper/723:20:5913
1913569994336,3cyclictest0-21swapper/722:04:0813
1913569994335,4cyclictest0-21swapper/723:06:2713
1913569994335,4cyclictest0-21swapper/721:53:5413
1913569994335,4cyclictest0-21swapper/721:43:5213
1913569994335,4cyclictest0-21swapper/721:20:0213
1913569994335,4cyclictest0-21swapper/719:40:5613
191356999430,39cyclictest976890-21kworker/7:2+mm_percpu_wq00:01:2013
1913569994239,3cyclictest0-21swapper/722:48:5013
1913569994238,0cyclictest0-21swapper/721:58:5813
1913569994238,0cyclictest0-21swapper/719:35:0413
1913569994235,3cyclictest0-21swapper/720:25:4613
1913569994234,4cyclictest976890-21kworker/7:2-mm_percpu_wq22:25:1213
1913569994234,4cyclictest976890-21kworker/7:2-mm_percpu_wq19:20:1613
1913569994234,4cyclictest976890-21kworker/7:2+mm_percpu_wq00:39:2013
1913569994234,4cyclictest0-21swapper/722:30:1013
1913569994234,4cyclictest0-21swapper/720:58:1813
1913569994234,4cyclictest0-21swapper/720:42:0913
1913569994234,4cyclictest0-21swapper/720:21:4613
1913569994234,4cyclictest0-21swapper/719:54:0213
1913569994234,4cyclictest0-21swapper/719:19:0613
191356999420,38cyclictest0-21swapper/723:48:5613
191356999420,38cyclictest0-21swapper/722:59:2013
191355299420,31cyclictest1677912-21kworker/2:1+mm_percpu_wq19:52:308
1913593994141,0cyclictest0-21swapper/1522:29:327
1913593994128,11cyclictest1972827-21DOM22:56:107
1913588994141,0cyclictest0-21swapper/1321:57:455
1913578994113,28cyclictest0-21swapper/1023:04:482
1913569994137,0cyclictest0-21swapper/700:07:3813
1913569994133,4cyclictest976890-21kworker/7:2-i915-unordered22:24:2413
1913569994133,4cyclictest0-21swapper/723:30:1713
1913569994133,4cyclictest0-21swapper/723:30:1713
1913569994133,4cyclictest0-21swapper/721:34:1813
1913569994133,4cyclictest0-21swapper/721:29:3613
1913569994133,4cyclictest0-21swapper/721:15:4413
1913569994133,4cyclictest0-21swapper/720:10:4213
1913569994133,4cyclictest0-21swapper/720:10:4213
1913569994133,4cyclictest0-21swapper/719:28:2613
191356799413,25cyclictest0-21swapper/621:46:5312
1913547994114,27cyclictest0-21swapper/023:04:480
1913569994037,3cyclictest0-21swapper/720:33:3613
1913569994036,0cyclictest0-21swapper/719:55:5413
1913569994033,3cyclictest0-21swapper/722:05:2013
1913569994032,4cyclictest0-21swapper/723:57:1213
1913569994032,4cyclictest0-21swapper/723:51:5213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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