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2023-09-26 - 20:36
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot4.osadl.org (updated Tue Sep 26, 2023 00:45:51)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
5572272435429,3sleep40-21swapper/419:05:4010
5573032434428,3sleep130-21swapper/1319:06:375
5572592434429,2sleep90-21swapper/919:06:0115
5572232432426,3sleep10-21swapper/119:05:371
5539612431426,2sleep70-21swapper/719:05:1113
5572162430425,2sleep140-21swapper/1419:05:346
5572772429425,2sleep100-21swapper/1019:06:182
5574302428423,2sleep50-21swapper/519:08:2111
5539592421416,2sleep60-21swapper/619:05:1012
5532662419414,2sleep120-21swapper/1219:05:004
5572262417413,2sleep30-21swapper/319:05:399
5574462416411,2sleep20-21swapper/219:08:348
5572582416411,2sleep80-21swapper/819:06:0014
5572612415410,2sleep110-21swapper/1119:06:033
5572652414409,2sleep150-21swapper/1519:06:077
5573072138137,0sleep00-21swapper/019:06:400
55797499453,21cyclictest0-21swapper/721:52:5213
557992994318,25cyclictest745532-21unixbench-2d22:30:364
55795099420,22cyclictest0-21swapper/121:52:521
557992993615,21cyclictest0-21swapper/1219:17:084
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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