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2024-02-25 - 12:22
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot4.osadl.org (updated Sun Feb 25, 2024 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
7720452369344,15sleep150-21swapper/1519:08:507
7721212363315,15sleep140-21swapper/1419:09:536
7718152358311,14sleep70-21swapper/719:05:4413
7718682354311,14sleep10-21swapper/119:06:271
7720082347322,15sleep30-21swapper/319:08:219
7720112345319,16sleep60-21swapper/619:08:2412
7719392342317,15sleep120-21swapper/1219:07:264
7718812342316,15sleep130-21swapper/1319:06:395
7685582342318,14sleep80-21swapper/819:05:1314
7720922341316,15sleep90-21swapper/919:09:3215
7720762341318,13sleep100-21swapper/1019:09:172
7719022341315,15sleep110-21swapper/1119:06:533
7718722341316,15sleep50-21swapper/519:06:3111
7718712341315,15sleep40-21swapper/419:06:3010
7719712340315,15sleep20-21swapper/219:07:488
7719692339314,15sleep00-21swapper/019:07:460
77251799456,25cyclictest0-21swapper/820:41:0014
77251799437,11cyclictest0-21swapper/823:14:4514
77251799426,11cyclictest0-21swapper/823:58:4114
77251799426,11cyclictest0-21swapper/822:19:5114
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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