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2023-01-28 - 12:14

x86 Intel Core i9-9900K @3600 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #0, slot #4
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4.osadl.org (updated Sat Jan 28, 2023 00:45:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
32156422407389,10sleep110-21swapper/1119:06:373
32156382377358,10sleep70-21swapper/719:06:3313
32156892356336,10sleep60-21swapper/619:07:2112
32155662340322,10sleep140-21swapper/1419:05:376
32145392339333,3sleep20-21swapper/219:05:248
32156882337319,10sleep50-21swapper/519:07:2011
32156162335315,12sleep120-21swapper/1219:06:224
32157942332313,10sleep80-21swapper/819:08:4414
32157442332314,10sleep10-21swapper/119:08:041
32156802332313,11sleep150-21swapper/1519:07:147
32158432329311,10sleep40-21swapper/419:09:2710
32155782329310,10sleep90-21swapper/919:05:4715
32123062329311,10sleep130-21swapper/1319:05:035
32155692326308,10sleep00-21swapper/019:05:380
32158062324306,10sleep30-21swapper/319:08:549
32158742323304,11sleep100-21swapper/1019:09:492
321631099283,25cyclictest0-21swapper/1522:25:397
321631099273,11cyclictest0-21swapper/1500:04:307
321631099262,11cyclictest0-21swapper/1522:03:417
321631099262,11cyclictest0-21swapper/1520:46:487
321631099240,11cyclictest0-21swapper/1519:51:537
3216310992110,3cyclictest0-21swapper/1520:50:247
321627599210,18cyclictest0-21swapper/520:06:4011
321630099200,17cyclictest0-21swapper/1219:48:434
321630099190,16cyclictest0-21swapper/1223:33:334
321629699190,16cyclictest0-21swapper/1122:55:163
321629299199,0cyclictest0-21swapper/1023:04:582
321631099180,18cyclictest0-21swapper/1522:12:407
321630099180,18cyclictest0-21swapper/1220:35:324
3216310991713,1cyclictest1697-21snmpd23:06:567
321631099170,17cyclictest0-21swapper/1520:05:207
321630799170,0cyclictest0-21swapper/1419:13:066
321630599170,14cyclictest0-21swapper/1300:27:445
321630099170,0cyclictest0-21swapper/1221:18:304
321629699170,14cyclictest0-21swapper/1120:31:443
321629699170,0cyclictest0-21swapper/1123:29:543
321629699170,0cyclictest0-21swapper/1122:34:473
321629299170,14cyclictest0-21swapper/1021:28:072
3216290991712,3cyclictest0-21swapper/922:10:1815
321629099170,14cyclictest0-21swapper/900:33:0315
321628199170,14cyclictest0-21swapper/722:25:0113
321628199170,14cyclictest0-21swapper/720:45:2613
321627899170,17cyclictest0-21swapper/623:44:2812
321627899170,17cyclictest0-21swapper/621:35:3112
321627199170,17cyclictest0-21swapper/423:00:4110
321626799170,17cyclictest0-21swapper/319:28:229
321626799170,17cyclictest0-21swapper/319:28:219
321626799170,14cyclictest0-21swapper/322:15:179
321626799170,14cyclictest0-21swapper/319:22:439
321626799170,14cyclictest0-21swapper/319:22:429
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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