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2025-05-12 - 23:15

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Mon May 12, 2025 00:46:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
39222222419397,14sleep40-21swapper/419:09:1410
39222222419397,14sleep40-21swapper/419:09:1410
39219722403396,4sleep10-21swapper/119:06:301
39219722403396,4sleep10-21swapper/119:06:291
39220162397391,4sleep100-21swapper/1019:06:552
39220162397391,4sleep100-21swapper/1019:06:552
39220182374335,12sleep110-21swapper/1119:06:563
39220182374335,12sleep110-21swapper/1119:06:563
39222662369362,5sleep00-21swapper/019:09:410
39222662369362,5sleep00-21swapper/019:09:410
39222042367328,12sleep60-21swapper/619:09:0012
39222042367328,12sleep60-21swapper/619:09:0012
39220432360343,10sleep150-21swapper/1519:07:167
39220432360343,10sleep150-21swapper/1519:07:167
39219262359341,11sleep130-21swapper/1319:05:545
39219262359341,11sleep130-21swapper/1319:05:535
39222062358336,14sleep80-21swapper/819:09:0214
39222062358336,14sleep80-21swapper/819:09:0214
39220152357338,12sleep90-21swapper/919:06:5415
39220152357338,12sleep90-21swapper/919:06:5415
39219442353333,13sleep120-21swapper/1219:06:094
39219442353333,13sleep120-21swapper/1219:06:094
39222722352332,13sleep30-21swapper/319:09:459
39222722352332,13sleep30-21swapper/319:09:459
39221502352332,13sleep70-21swapper/719:08:2813
39221502352332,13sleep70-21swapper/719:08:2813
39221072350330,13sleep50-21swapper/519:07:5311
39221072350330,13sleep50-21swapper/519:07:5311
39221042349329,13sleep20-21swapper/219:07:518
39221042349329,13sleep20-21swapper/219:07:518
39221612345325,13sleep140-21swapper/1419:08:356
39221612345325,13sleep140-21swapper/1419:08:346
3922752995252,0cyclictest0-21swapper/422:47:2910
3922772994640,6cyclictest0-21swapper/922:47:2915
392277299389,26cyclictest38289-21kworker/9:0+events23:38:4115
3922772993838,0cyclictest0-21swapper/921:30:4115
3922752993737,0cyclictest0-21swapper/421:30:4010
392275899360,35cyclictest0-21swapper/622:25:1512
3922752993632,1cyclictest0-21swapper/421:00:2110
3922772993529,6cyclictest0-21swapper/922:21:5315
392279199344,29cyclictest3955880-21kworker/u32:2+events_unbound19:57:397
392279199341,30cyclictest4019523-21kworker/u32:3+flush-259:020:35:157
3922772993434,0cyclictest0-21swapper/923:47:1915
392275899340,1cyclictest0-21swapper/620:05:1812
3922752993427,7cyclictest0-21swapper/422:21:5310
3922791993330,3cyclictest4019523-21kworker/u32:3+events_unbound21:35:477
3922758993329,4cyclictest1813-21snmpd19:20:1612
392279199322,27cyclictest129381-21kworker/u32:0+events_unbound00:26:277
392279199320,29cyclictest0-21swapper/1520:23:397
392278299320,29cyclictest0-21swapper/1222:15:164
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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