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2024-04-19 - 23:33

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Fri Apr 19, 2024 00:46:55)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31319422384378,4sleep20-21swapper/219:07:188
31319952373351,14sleep130-21swapper/1319:08:035
31321102371351,13sleep80-21swapper/819:09:0214
31320572364345,12sleep30-21swapper/319:08:259
31321482363355,5sleep50-21swapper/519:09:3111
31321162347323,15sleep140-21swapper/1419:09:086
31320872347325,15sleep60-21swapper/619:08:4412
31320702347324,15sleep120-21swapper/1219:08:344
31318462347325,15sleep90-21swapper/919:06:0615
31320272346323,15sleep70-21swapper/719:08:1213
31321782345324,14sleep150-21swapper/1519:09:577
31319702345322,15sleep110-21swapper/1119:07:443
31318582344321,15sleep40-21swapper/419:06:1710
31319922343321,15sleep100-21swapper/1019:07:592
31321022342320,15sleep00-21swapper/019:08:540
31320022342321,14sleep10-21swapper/119:08:071
3132579995049,1cyclictest0-21swapper/421:13:3310
3132597994645,1cyclictest3171180-21kworker/u32:0+flush-259:019:55:302
3132582994610,11cyclictest0-21swapper/520:05:4011
3132610994039,1cyclictest3491927-21kworker/u32:3+events_unbound23:25:176
3132582993938,0cyclictest0-21swapper/500:02:4911
3132579993732,5cyclictest0-21swapper/423:43:0910
3132579993732,5cyclictest0-21swapper/423:43:0910
3132610993635,1cyclictest3230187-21kworker/u32:0+events_unbound21:05:236
3132600993635,1cyclictest3415634-21kworker/u32:5+flush-259:023:15:213
3132566993635,1cyclictest3424419-21kworker/u32:3+events_unbound22:42:540
3132610993535,0cyclictest0-21swapper/1400:20:036
3132610993535,0cyclictest0-21swapper/1400:09:316
3132610993534,1cyclictest3251147-21kworker/u32:4+events_unbound20:55:216
3132582993535,0cyclictest0-21swapper/523:57:3111
3132591993434,0cyclictest0-21swapper/823:56:0314
3132591993434,0cyclictest0-21swapper/823:07:0714
3132591993434,0cyclictest0-21swapper/820:38:0114
3132591993433,1cyclictest3436994-21kworker/8:2-events23:40:5914
3132591993433,1cyclictest3436994-21kworker/8:2-events23:40:5914
3132591993433,1cyclictest3415634-21kworker/u32:5+events_unbound22:55:2114
3132589993433,1cyclictest3415634-21kworker/u32:5+events_unbound22:30:2613
3132582993434,0cyclictest0-21swapper/520:27:3311
3132582993434,0cyclictest0-21swapper/520:27:3311
3132582993410,11cyclictest0-21swapper/521:44:3111
3132573993434,0cyclictest0-21swapper/221:01:208
3132573993433,1cyclictest3584770-21kworker/u32:0+events_unbound00:30:218
3132595993333,0cyclictest0-21swapper/900:07:2715
3132591993333,0cyclictest0-21swapper/820:48:5114
3132591993333,0cyclictest0-21swapper/819:57:4114
3132591993329,4cyclictest0-21swapper/800:02:4914
313258999330,32cyclictest0-21swapper/722:00:1613
313258299339,11cyclictest0-21swapper/522:17:2811
313258299339,11cyclictest0-21swapper/519:54:4111
313258299339,11cyclictest0-21swapper/519:10:4511
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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