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2024-12-10 - 06:11

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Tue Dec 10, 2024 00:46:39)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
15287992434390,13sleep100-21swapper/1019:08:402
15287612383376,4sleep120-21swapper/1219:08:104
15287012371330,13sleep140-21swapper/1419:07:226
15286952366343,13sleep90-21swapper/919:07:1815
15285682362354,5sleep130-21swapper/1319:05:305
15286872361317,14sleep10-21swapper/119:07:091
15286172356335,12sleep80-21swapper/819:06:1314
15288232355333,13sleep150-21swapper/1519:09:007
15286562355312,14sleep60-21swapper/619:06:4212
15287692353332,13sleep30-21swapper/319:08:179
15288362352332,12sleep110-21swapper/1119:09:133
15286522352332,12sleep20-21swapper/219:06:398
15286742350328,13sleep50-21swapper/519:06:5711
15288462349326,14sleep40-21swapper/419:09:2210
15286592345322,14sleep70-21swapper/719:06:4413
15288252344320,14sleep00-21swapper/019:09:010
15292849910629,75cyclictest0-21swapper/123:05:231
174259121040,1sleep2411rcuc/221:55:098
174259121040,1sleep2411rcuc/221:55:098
15292809910343,28cyclictest0-21swapper/019:38:290
15292999910231,43cyclictest0-21swapper/619:38:2912
15292809910144,28cyclictest0-21swapper/023:05:220
152932599998,90cyclictest0-21swapper/1423:05:216
1529299999435,28cyclictest0-21swapper/621:40:0212
1529309999032,29cyclictest0-21swapper/919:38:2815
1529289998728,59cyclictest0-21swapper/321:40:019
1529284998612,74cyclictest0-21swapper/119:38:291
1529319998427,28cyclictest0-21swapper/1219:38:284
1529319998426,28cyclictest0-21swapper/1221:40:024
152930699827,75cyclictest0-21swapper/821:40:0214
1529299998223,30cyclictest0-21swapper/623:05:2212
152932199798,44cyclictest0-21swapper/1323:05:235
1529296997921,28cyclictest0-21swapper/521:40:0111
1529309997850,28cyclictest0-21swapper/923:05:2315
1529294997212,29cyclictest0-21swapper/421:40:0210
152929699710,44cyclictest0-21swapper/519:38:2911
1529294997170,1cyclictest3502-21Xorg19:38:2810
1529321997069,1cyclictest3502-21Xorg21:40:015
1529296996767,0cyclictest3502-21Xorg23:05:2311
1529315995450,1cyclictest3502-21Xorg21:40:003
1529304995151,0cyclictest0-21swapper/723:05:2213
1529327994848,0cyclictest3502-21Xorg23:05:227
1529280994746,1cyclictest3502-21Xorg21:40:020
1529325994545,0cyclictest0-21swapper/1421:40:026
152932599440,43cyclictest0-21swapper/1419:38:286
152929999416,10cyclictest0-21swapper/621:30:2412
1529319994040,0cyclictest1641853-21kworker/12:0-events22:55:134
1529304994038,2cyclictest3502-21Xorg19:38:2913
1529306993837,1cyclictest3502-21Xorg19:38:2914
152929499376,31cyclictest0-21swapper/423:05:2210
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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