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2026-04-18 - 09:04

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #4

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot4s.osadl.org (updated Sat Apr 18, 2026 00:46:19)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
8734342406400,4sleep10-21swapper/119:09:491
8734292392373,17sleep130-21swapper/1319:09:455
8733092369351,11sleep30-21swapper/319:08:139
8732702367325,13sleep40-21swapper/419:07:4310
8733082361341,13sleep20-21swapper/219:08:128
8732912358338,13sleep80-21swapper/819:08:0314
8731492357337,13sleep50-21swapper/519:06:0811
8733432355337,12sleep90-21swapper/919:08:3615
8732892352333,13sleep60-21swapper/619:08:0112
8731362352332,13sleep150-21swapper/1519:06:027
8732362351330,14sleep100-21swapper/1019:07:162
8733452348327,13sleep110-21swapper/1119:08:393
8732902348328,13sleep70-21swapper/719:08:0213
8731352348327,14sleep140-21swapper/1419:06:016
8733872347326,14sleep120-21swapper/1219:09:124
8732472343322,14sleep00-21swapper/019:07:230
87395699545,24cyclictest975445-21diskmemload00:16:476
873956994624,10cyclictest0-21swapper/1419:53:116
87395699446,25cyclictest0-21swapper/1422:48:556
87395699426,25cyclictest0-21swapper/1421:21:026
873921994241,1cyclictest1108544-21kworker/u32:1+events_unbound22:58:138
873921994212,0cyclictest0-21swapper/219:10:098
873921994140,1cyclictest1024609-21kworker/u32:0+events_unbound21:59:538
87395699404,11cyclictest0-21swapper/1422:59:546
87395699404,11cyclictest0-21swapper/1420:59:056
87395699404,11cyclictest0-21swapper/1420:37:076
87395699404,11cyclictest0-21swapper/1420:37:076
873921994038,2cyclictest1037713-21kworker/u32:5+events_unbound22:22:398
873921993938,1cyclictest1024609-21kworker/u32:0+events_unbound21:47:058
873921993936,3cyclictest1052923-21kworker/u32:0+events_unbound23:03:538
87395699383,10cyclictest0-21swapper/1421:10:046
873956993825,0cyclictest0-21swapper/1423:32:516
873921993834,4cyclictest1089315-21kworker/u32:3+events_unbound22:38:198
873934993728,8cyclictest1035906-21mii-tool21:55:1312
873921993733,0cyclictest211rcu_preempt00:30:518
873961993636,0cyclictest0-21swapper/1521:25:117
873915993613,1cyclictest0-21swapper/021:37:130
873956993535,0cyclictest0-21swapper/1423:17:196
873956993535,0cyclictest0-21swapper/1421:55:336
87395699350,10cyclictest0-21swapper/1423:21:526
873934993528,1cyclictest1774-21snmpd22:58:5512
873921993534,1cyclictest0-21swapper/221:37:358
873921993533,2cyclictest0-21swapper/223:49:418
873921993533,2cyclictest0-21swapper/223:49:418
873921993533,2cyclictest0-21swapper/223:25:558
87392199353,30cyclictest0-21swapper/223:37:078
873921993533,0cyclictest0-21swapper/223:15:418
873921993533,0cyclictest0-21swapper/222:17:338
873921993532,3cyclictest0-21swapper/223:10:538
873961993434,0cyclictest0-21swapper/1500:39:277
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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