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2024-05-26 - 08:50
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sun May 26, 2024 00:43:44)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
128607999739739,0cyclictest0-21swapper/520:49:5311
128611399551549,2cyclictest1417143-21kworker/14:2+i915-unordered23:06:526
12860799954497,445cyclictest1426957-21kworker/5:1+events23:15:1511
128610199539538,1cyclictest1185022-21kworker/11:0+i915-unordered20:54:303
12860669953623,25cyclictest0-21swapper/101:48:151
1286063995366,25cyclictest0-21swapper/022:47:140
128607699535505,30cyclictest0-21swapper/400:29:5310
12860969953420,25cyclictest0-21swapper/1021:53:142
12860799953159,472cyclictest0-21swapper/501:24:5211
12861159952620,505cyclictest0-21swapper/1521:24:547
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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