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2024-12-10 - 23:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Tue Dec 10, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
336497999537537,0cyclictest0-21swapper/1123:49:333
336496499534533,1cyclictest0-21swapper/600:23:1112
336498999531529,1cyclictest3479383-21kworker/14:0+events00:23:116
336499399525524,1cyclictest3385336-21kworker/15:1+i915-unordered20:52:117
336497499524100,422cyclictest3278798-21kworker/9:2+i915-unordered21:42:3215
336497499518109,407cyclictest3432363-21kworker/9:1+events21:56:3215
336497999517488,29cyclictest0-21swapper/1123:35:323
336497999517488,29cyclictest0-21swapper/1123:35:323
33649749951390,423cyclictest3440038-21kworker/9:0+events22:56:1215
33649749950834,0cyclictest0-21swapper/923:37:1215
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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