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2026-01-18 - 00:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Jan 17, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3085349950113,487cyclictest0-21swapper/423:47:5410
3085249949722,27cyclictest0-21swapper/122:04:541
30852799485484,1cyclictest508463-21kworker/2:1+i915-unordered23:16:548
3085249948414,29cyclictest0-21swapper/121:39:541
30853499473472,1cyclictest436488-21kworker/4:0+i915-unordered21:39:5410
3085249946111,29cyclictest0-21swapper/100:11:541
308553994599,58cyclictest0-21swapper/922:13:5015
3085589945726,30cyclictest0-21swapper/1022:34:542
30852799450450,0cyclictest0-21swapper/200:26:188
30855399449447,1cyclictest580364-21updatedb00:26:1815
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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