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2026-05-10 - 17:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sun May 10, 2026 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
28532995765,42cyclictest0-21swapper/420:00:2210
28541995575,551cyclictest0-21swapper/620:10:2212
2852299550549,1cyclictest3906424-21kworker/1:3+i915-unordered19:34:231
285749953716,521cyclictest0-21swapper/1421:00:226
2857499533531,2cyclictest77563-21kworker/14:0+i915-unordered20:10:226
2857199526525,1cyclictest149961-21kworker/13:0+i915-unordered21:41:225
285719951527,487cyclictest0-21swapper/1321:35:225
2855199511509,2cyclictest210128-21kworker/9:1+i915-unordered22:57:2215
285519950121,58cyclictest0-21swapper/919:49:0615
285649949837,461cyclictest0-21swapper/1121:45:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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