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2025-07-02 - 07:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Wed Jul 02, 2025 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246085299734316,416cyclictest0-21swapper/323:20:049
246086199551549,2cyclictest2699951-21kworker/5:2+i915-unordered00:01:2011
24608859955012,536cyclictest0-21swapper/1123:40:203
246086199523522,1cyclictest2498555-21kworker/5:1+i915-unordered20:16:2011
246085699517516,0cyclictest1951382-21kworker/4:3+i915-unordered19:15:2110
246086199516515,1cyclictest2650666-21kworker/5:0+i915-unordered23:00:2011
246089599515484,31cyclictest0-21swapper/1323:00:205
246086199503503,0cyclictest0-21swapper/521:12:2011
246089599502502,0cyclictest2547879-21kworker/13:2+i915-unordered21:12:205
246085299502501,1cyclictest2580605-21kworker/3:2+i915-unordered21:38:209
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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