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2024-09-07 - 17:31
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack0slot5.osadl.org (updated Sat Sep 07, 2024 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
133691299676675,1cyclictest1303722-21kworker/13:2+events20:59:485
133687699572561,1cyclictest0-21swapper/201:13:108
133687699556555,1cyclictest0-21swapper/201:44:118
133688899555555,0cyclictest0-21swapper/601:41:1112
1336882995520,552cyclictest0-21swapper/423:45:4810
133690599551549,2cyclictest1490617-21kworker/12:0+i915-unordered23:45:484
133688899547547,0cyclictest0-21swapper/600:42:1212
13369129954441,0cyclictest0-21swapper/1300:24:485
13369129954439,504cyclictest0-21swapper/1322:44:255
133687699543543,0cyclictest0-21swapper/201:52:098
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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