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2025-07-19 - 13:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Sat Jul 19, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
41746472383371,7sleep120-21swapper/1219:06:414
41746322377369,5sleep140-21swapper/1419:06:266
41713732375366,5sleep50-21swapper/519:03:5311
41746792364356,5sleep70-21swapper/719:07:0813
41744822357347,6sleep110-21swapper/1119:04:153
41746362355346,5sleep10-21swapper/119:06:291
41745082350327,13sleep150-21swapper/1519:04:357
41747722346335,6sleep40-21swapper/419:08:2510
41747282343332,6sleep30-21swapper/319:07:529
41746442341316,15sleep90-21swapper/919:06:3715
41747182338326,7sleep100-21swapper/1019:07:432
41746262327301,16sleep80-21swapper/819:06:2014
41745762327300,17sleep130-21swapper/1319:05:375
41745462275267,5sleep00-21swapper/019:05:080
41745292195187,4sleep20-21swapper/219:04:548
417511399567,25cyclictest0-21swapper/523:02:5311
417511399567,25cyclictest0-21swapper/523:02:5311
4175090995231,11cyclictest125173-21timerandwakeup21:59:130
417511399500,39cyclictest0-21swapper/521:56:5911
417511399500,25cyclictest0-21swapper/523:57:4811
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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