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2026-02-09 - 15:14
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Mon Feb 09, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3407459946515,59cyclictest0-21swapper/821:45:3814
3407269945027,29cyclictest0-21swapper/320:03:559
3407339944825,30cyclictest70-21ksoftirqd/522:55:5511
3407339944825,30cyclictest70-21ksoftirqd/522:55:5511
3407649944624,31cyclictest0-21swapper/1223:06:554
3407649944624,31cyclictest0-21swapper/1223:06:554
3407269944620,29cyclictest0-21swapper/320:49:519
3407669944526,28cyclictest0-21swapper/1300:11:555
3407339944522,29cyclictest70-21ksoftirqd/520:36:5511
3407669944424,30cyclictest0-21swapper/1323:38:555
3407549944424,30cyclictest0-21swapper/1019:58:552
3407549944324,30cyclictest0-21swapper/1021:53:552
3407289944224,418cyclictest0-21swapper/420:30:1810
3407369944114,30cyclictest0-21swapper/619:37:1812
3407369944015,30cyclictest0-21swapper/620:17:1712
3407369944014,29cyclictest0-21swapper/620:20:4012
3407369944013,30cyclictest0-21swapper/622:22:4012
3407289944020,419cyclictest0-21swapper/420:55:1610
3407369943913,30cyclictest0-21swapper/620:59:1812
3407369943913,28cyclictest0-21swapper/621:16:4212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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