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2023-10-01 - 00:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot5.osadl.org (updated Sat Sep 30, 2023 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
13731932361354,4sleep00-21swapper/019:04:180
13762012356350,3sleep120-21swapper/1219:06:064
13763512350314,10sleep20-21swapper/219:08:218
13763292345308,11sleep140-21swapper/1419:08:016
13762542342323,11sleep100-21swapper/1019:06:532
13761752342324,10sleep60-21swapper/619:05:4412
13761432341322,11sleep130-21swapper/1319:05:195
13763472340332,4sleep150-21swapper/1519:08:187
13731972340322,10sleep40-21swapper/419:04:2210
13761712338301,10sleep30-21swapper/319:05:419
13763962335317,10sleep90-21swapper/919:09:0015
13762282335317,10sleep50-21swapper/519:06:3111
13761382334316,10sleep80-21swapper/819:05:1414
13763432333315,10sleep110-21swapper/1119:08:143
13761372333315,10sleep70-21swapper/719:05:1313
13761482323306,10sleep10-21swapper/119:05:231
1376696997816,42cyclictest0-21swapper/223:50:238
1376699997517,1cyclictest0-21swapper/321:44:599
1376696997232,20cyclictest1672733-21cpuspeed_turbos23:59:278
137669699718,42cyclictest0-21swapper/222:27:578
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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