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2026-02-11 - 02:31
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Wed Feb 11, 2026 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
85682499721299,419cyclictest0-21swapper/1300:25:345
8568289951817,469cyclictest0-21swapper/1420:13:516
8568289951817,469cyclictest0-21swapper/1420:13:516
8568199950518,27cyclictest0-21swapper/1220:26:514
85677899493490,2cyclictest949897-21kworker/2:2+i915-unordered21:30:518
85681999489487,1cyclictest1002224-21kworker/12:0+i915-unordered22:08:514
8568199948812,475cyclictest0-21swapper/1221:02:514
8568199947614,461cyclictest0-21swapper/1223:02:514
8568199947614,461cyclictest0-21swapper/1223:02:514
856791994696,462cyclictest0-21swapper/522:42:5111
856819994655,460cyclictest0-21swapper/1221:28:514
856819994654,460cyclictest0-21swapper/1221:21:514
8568019946518,30cyclictest0-21swapper/819:41:3714
85683199463462,1cyclictest978142-21kworker/15:1+i915-unordered21:53:517
8568249946318,58cyclictest0-21swapper/1323:16:515
85679199461460,1cyclictest1046624-21kworker/5:4+i915-unordered23:51:5111
856828994567,30cyclictest0-21swapper/1423:49:346
856815994567,29cyclictest0-21swapper/1100:24:143
85681099454452,2cyclictest0-21swapper/1021:30:512
856815994534,30cyclictest0-21swapper/1120:10:143
856815994534,30cyclictest0-21swapper/1120:10:143
85677599453451,2cyclictest966098-21kworker/1:1+i915-unordered21:28:511
856828994523,30cyclictest0-21swapper/1420:32:146
85683199451448,2cyclictest982174-21kworker/15:0+pm22:08:037
8568289944922,30cyclictest0-21swapper/1421:18:356
85679199449448,1cyclictest0-21swapper/500:20:5111
856828994480,30cyclictest0-21swapper/1423:41:346
856828994480,29cyclictest0-21swapper/1421:14:386
856824994470,30cyclictest0-21swapper/1319:30:515
856828994460,29cyclictest0-21swapper/1421:00:146
856810994460,53cyclictest0-21swapper/1021:40:512
8567869944617,427cyclictest0-21swapper/419:45:1310
85682899445444,1cyclictest1801-21snmpd22:20:486
856828994440,30cyclictest0-21swapper/1421:43:356
8568019944423,29cyclictest0-21swapper/823:59:3614
85678699443439,4cyclictest1801-21snmpd23:04:2610
85678699443439,4cyclictest1801-21snmpd23:04:2610
85680199442442,0cyclictest0-21swapper/823:53:1414
8567919944222,419cyclictest0-21swapper/500:10:1411
85681599441434,6cyclictest1801-21snmpd22:29:043
85680199441441,0cyclictest0-21swapper/823:48:1414
8567979944120,420cyclictest0-21swapper/723:23:1313
8567869944123,417cyclictest0-21swapper/423:14:4710
856824994400,30cyclictest0-21swapper/1320:37:515
856819994400,439cyclictest0-21swapper/1223:47:514
8567869944021,418cyclictest0-21swapper/423:54:3510
856786994400,30cyclictest0-21swapper/423:57:1410
85677299440439,1cyclictest0-21swapper/020:16:510
8568289943921,28cyclictest0-21swapper/1419:35:516
8568159943919,419cyclictest0-21swapper/1121:10:133
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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