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2024-12-10 - 20:11
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Tue Dec 10, 2024 00:43:41)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
336497999537537,0cyclictest0-21swapper/1123:49:333
336496499534533,1cyclictest0-21swapper/600:23:1112
336498999531529,1cyclictest3479383-21kworker/14:0+events00:23:116
336499399525524,1cyclictest3385336-21kworker/15:1+i915-unordered20:52:117
336497499524100,422cyclictest3278798-21kworker/9:2+i915-unordered21:42:3215
336497499518109,407cyclictest3432363-21kworker/9:1+events21:56:3215
336497999517488,29cyclictest0-21swapper/1123:35:323
336497999517488,29cyclictest0-21swapper/1123:35:323
33649749951390,423cyclictest3440038-21kworker/9:0+events22:56:1215
33649749950834,0cyclictest0-21swapper/923:37:1215
33649749950834,0cyclictest0-21swapper/923:37:1215
3364974995069,45cyclictest105-21ksoftirqd/921:15:1115
33649749950554,0cyclictest0-21swapper/920:58:3415
3364974995048,496cyclictest105-21ksoftirqd/901:31:3415
33649469950321,482cyclictest0-21swapper/020:51:330
336497999502501,1cyclictest0-21swapper/1101:22:483
33649749950151,0cyclictest0-21swapper/923:13:1015
33649749950148,0cyclictest0-21swapper/901:04:1215
33649749950118,42cyclictest0-21swapper/900:19:3315
3364974995005,45cyclictest105-21ksoftirqd/900:43:3215
3364974994993,46cyclictest105-21ksoftirqd/921:46:1215
33649749949876,421cyclictest3613789-21kworker/9:1+i915-unordered01:43:1115
33649939949714,0cyclictest0-21swapper/1521:28:137
33649469949714,482cyclictest0-21swapper/000:10:110
3364977994960,496cyclictest0-21swapper/1000:15:102
33649749949645,451cyclictest0-21swapper/921:29:1215
336496799496494,2cyclictest0-21swapper/720:52:1113
336497499495495,0cyclictest0-21swapper/920:41:1015
33649749949545,450cyclictest0-21swapper/923:24:4815
33649749949545,450cyclictest0-21swapper/923:24:4815
33649749949542,452cyclictest0-21swapper/922:21:4815
33649749949512,44cyclictest0-21swapper/900:57:1315
33649749949443,451cyclictest0-21swapper/923:43:1015
33649749949441,453cyclictest0-21swapper/921:38:3315
33649749949441,451cyclictest0-21swapper/901:52:1215
33649749949341,451cyclictest0-21swapper/922:05:3415
33649749949241,451cyclictest0-21swapper/922:14:1215
33649749949241,450cyclictest0-21swapper/900:06:1215
33649749949238,452cyclictest0-21swapper/900:36:1215
33649749949141,450cyclictest0-21swapper/900:46:3415
33649749949138,451cyclictest0-21swapper/922:47:3415
3364957994918,483cyclictest0-21swapper/400:25:4810
336495799491491,0cyclictest0-21swapper/423:03:3410
33649749949053,436cyclictest0-21swapper/921:22:1015
33649749949046,442cyclictest0-21swapper/900:10:1115
33649749949041,0cyclictest791149-21avahi-daemon01:45:1015
33649749949040,450cyclictest0-21swapper/922:30:1115
33649749949040,449cyclictest0-21swapper/923:00:1115
33649749949040,0cyclictest0-21swapper/920:24:1315
33649749949039,451cyclictest0-21swapper/922:42:3515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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