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2023-06-06 - 19:30

x86 Intel Core i7-3770K @3500 MHz, Linux 5.15.49-rt47 (Profile)

Latency plot of system in rack #0, slot #5
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Tue Jun 06, 2023 00:43:37)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21663962340332,4sleep40-21swapper/418:59:2710
21665662337329,4sleep70-21swapper/719:01:5413
21664872334326,4sleep20-21swapper/219:00:458
21664772332314,10sleep90-21swapper/919:00:3615
21664742331311,12sleep60-21swapper/619:00:3312
21664552329311,11sleep80-21swapper/819:00:1914
21664032328310,10sleep110-21swapper/1118:59:343
21666382327309,10sleep120-21swapper/1219:02:484
21666562326306,10sleep100-21swapper/1019:03:022
21664612326306,11sleep140-21swapper/1419:00:256
21664502326305,11sleep30-21swapper/319:00:149
21665952324306,10sleep150-21swapper/1519:02:197
21664342323304,11sleep50-21swapper/519:00:0011
21663752323303,10sleep00-21swapper/018:59:070
21665222322302,10sleep10-21swapper/119:01:161
21664062321303,10sleep130-21swapper/1318:59:365
2167009999612,42cyclictest0-21swapper/1321:13:295
2167009999612,42cyclictest0-21swapper/1319:31:255
2167009998421,21cyclictest52950usb-storage20:49:335
2166961998117,42cyclictest2395739-21ssh22:56:171
2167009997715,21cyclictest2187488-21latency_hist19:28:155
2167009997714,42cyclictest0-21swapper/1321:20:015
2167009997613,63cyclictest0-21swapper/1320:58:135
2167009997513,41cyclictest0-21swapper/1322:23:435
2167009997513,20cyclictest0-21swapper/1320:08:315
2167009997210,20cyclictest2508209-21ssh00:30:415
216700999675,20cyclictest2448845-21ssh23:40:455
216700999663,21cyclictest0-21swapper/1321:38:295
2166961996538,20cyclictest10792-21SPICE14:13:091
216700999642,21cyclictest2461147-21ssh23:51:435
2166961996338,25cyclictest426019-21containerd21:06:251
2167009996117,22cyclictest0-21swapper/1323:07:295
2167009996117,22cyclictest0-21swapper/1322:30:315
216700999610,19cyclictest0-21swapper/1321:47:055
2166987996015,45cyclictest0-21swapper/821:11:4114
2167009995917,0cyclictest0-21swapper/1323:13:215
2167009995917,0cyclictest0-21swapper/1300:08:335
2167009995917,0cyclictest0-21swapper/1300:08:335
216700999590,17cyclictest0-21swapper/1322:59:415
2166987995914,45cyclictest0-21swapper/823:47:1914
2166987995914,45cyclictest0-21swapper/819:09:5914
216696199590,0cyclictest0-21swapper/121:13:291
2167009995817,21cyclictest0-21swapper/1323:45:055
2167009995817,21cyclictest0-21swapper/1322:14:455
2167009995817,21cyclictest0-21swapper/1322:08:495
2167009995817,21cyclictest0-21swapper/1321:35:135
2167009995817,21cyclictest0-21swapper/1320:45:435
2167009995817,21cyclictest0-21swapper/1320:33:175
2167009995817,21cyclictest0-21swapper/1320:29:335
2167009995817,0cyclictest0-21swapper/1323:23:515
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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