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2023-09-28 - 14:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Thu Sep 28, 2023 00:43:36)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17569572361356,3sleep60-21swapper/619:05:2112
17548762351345,3sleep90-21swapper/919:04:3615
17569452349343,3sleep120-21swapper/1219:05:114
17571252344308,10sleep70-21swapper/719:07:4713
17571312341322,11sleep130-21swapper/1319:07:535
17570602341323,10sleep140-21swapper/1419:06:506
17572112340322,10sleep50-21swapper/519:09:0511
17571632338319,11sleep110-21swapper/1119:08:233
17570352338304,26sleep100-21swapper/1019:06:292
17570122336318,10sleep40-21swapper/419:06:0710
17570822333315,10sleep20-21swapper/219:07:108
17570112333315,10sleep30-21swapper/319:06:069
17571672332314,10sleep150-21swapper/1519:08:277
17569802332315,10sleep80-21swapper/819:05:3914
17570982328310,10sleep10-21swapper/119:07:251
17540152323305,10sleep00-21swapper/019:04:270
17575109911915,42cyclictest52250usb-storage21:36:448
1757510998422,62cyclictest1797111-21ntpq19:59:388
1757527997816,21cyclictest0-21swapper/621:36:4412
175752799686,42cyclictest0-21swapper/622:41:1212
175752799663,21cyclictest0-21swapper/622:34:2612
1757510995917,42cyclictest0-21swapper/221:10:488
1757510995915,19cyclictest141rcu_preempt20:09:388
175751099590,17cyclictest0-21swapper/221:56:568
175751099590,17cyclictest0-21swapper/220:38:488
1757527995836,22cyclictest0-21swapper/622:24:3412
1757527995816,42cyclictest0-21swapper/623:12:0412
1757527995816,21cyclictest0-21swapper/621:41:3612
1757510995817,21cyclictest0-21swapper/200:37:008
1757510995817,0cyclictest0-21swapper/200:27:328
1757510995816,42cyclictest0-21swapper/222:59:448
1757510995816,42cyclictest0-21swapper/222:18:108
1757527995716,21cyclictest0-21swapper/623:52:4012
1757527995715,42cyclictest0-21swapper/622:57:4412
1757510995715,42cyclictest0-21swapper/221:39:208
1757510995714,42cyclictest0-21swapper/222:14:028
1757510995713,42cyclictest0-21swapper/222:57:288
1757527995614,42cyclictest0-21swapper/620:27:3012
1757510995615,21cyclictest1865396-21ssh21:21:308
1757510995614,42cyclictest0-21swapper/223:45:288
1757510995515,20cyclictest2090521-21ssh00:32:448
1757510995514,21cyclictest1873458-21sh21:29:388
1757510995513,42cyclictest0-21swapper/223:05:308
1757510995512,21cyclictest0-21swapper/222:25:368
1757510995510,21cyclictest0-21swapper/200:10:008
1757527995412,42cyclictest0-21swapper/620:30:5812
1757510995414,20cyclictest2019355-21ssh23:32:128
1757510995414,20cyclictest2019355-21ssh23:32:128
1757510995412,42cyclictest0-21swapper/221:44:508
1757510995412,42cyclictest0-21swapper/219:58:348
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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