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2024-03-01 - 19:55
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5.osadl.org (updated Fri Mar 01, 2024 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
48484699603603,0cyclictest0-21swapper/000:19:430
48484699601601,0cyclictest0-21swapper/020:50:570
48484699597597,0cyclictest0-21swapper/020:27:570
48484699590590,0cyclictest0-21swapper/022:03:440
48484699588587,1cyclictest0-21swapper/023:58:570
48484699586586,0cyclictest0-21swapper/000:14:210
48484699582581,1cyclictest0-21swapper/022:38:200
48484699582581,1cyclictest0-21swapper/022:34:200
48484699581580,1cyclictest0-21swapper/020:21:570
48484699580580,0cyclictest0-21swapper/023:24:420
48486699555555,0cyclictest0-21swapper/720:15:2213
4848569953538,497cyclictest0-21swapper/400:28:4110
4848669953336,497cyclictest0-21swapper/722:50:2013
4848669952816,26cyclictest0-21swapper/700:04:5413
4848719952626,500cyclictest0-21swapper/923:40:2015
4848719952626,498cyclictest0-21swapper/920:38:4315
4848469952543,481cyclictest17-21ksoftirqd/000:24:410
4848959952223,499cyclictest0-21swapper/1500:35:577
4848669952119,57cyclictest0-21swapper/720:14:2013
4848669952039,480cyclictest569718-21kworker/u32:2-events_unbound20:49:4313
4848919951851,465cyclictest0-21swapper/1422:04:436
4848919951724,493cyclictest0-21swapper/1400:25:436
484850995166,26cyclictest0-21swapper/219:27:438
4848609951413,500cyclictest0-21swapper/519:21:4111
4848469951024,481cyclictest0-21swapper/019:28:210
4848919950822,56cyclictest0-21swapper/1421:33:206
4848919950821,486cyclictest0-21swapper/1419:39:436
4848529950718,488cyclictest0-21swapper/321:12:439
484847995070,27cyclictest0-21swapper/119:58:571
484881995056,27cyclictest0-21swapper/1221:45:454
4848509950520,43cyclictest0-21swapper/200:13:428
4848509950513,57cyclictest0-21swapper/223:21:438
484895995046,497cyclictest0-21swapper/1520:09:447
4848919950323,1cyclictest0-21swapper/1423:29:416
4848819950314,56cyclictest0-21swapper/1200:00:574
4848919950111,490cyclictest0-21swapper/1400:07:416
48485099500499,1cyclictest0-21swapper/222:14:208
48485099500499,1cyclictest0-21swapper/200:17:578
4848469950045,451cyclictest0-21swapper/021:12:190
4848469950012,70cyclictest0-21swapper/020:18:570
4848669949912,82cyclictest0-21swapper/723:45:2013
48489599498496,2cyclictest630757-21kworker/15:0+events21:47:437
4848789949849,449cyclictest0-21swapper/1120:56:573
4848469949847,0cyclictest0-21swapper/022:55:210
4848469949753,443cyclictest0-21swapper/019:38:420
4848469949748,0cyclictest0-21swapper/020:05:220
4848469949715,28cyclictest0-21swapper/000:28:410
484891994968,57cyclictest0-21swapper/1420:06:206
484891994966,59cyclictest0-21swapper/1421:20:216
484891994958,0cyclictest0-21swapper/1419:45:206
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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