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2024-04-19 - 23:37

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #5

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot5s.osadl.org (updated Fri Apr 19, 2024 00:45:15)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14813562435429,4sleep90-21swapper/919:07:3915
14814822422416,4sleep110-21swapper/1119:09:333
14814432402396,4sleep60-21swapper/619:08:5612
14813912402396,4sleep80-21swapper/819:08:1114
14813662401395,4sleep20-21swapper/219:07:488
14812192399393,4sleep150-21swapper/1519:05:377
14812162399393,4sleep120-21swapper/1219:05:344
14812142399393,4sleep100-21swapper/1019:05:312
14813302398392,4sleep00-21swapper/019:07:130
14813162398391,4sleep30-21swapper/319:07:009
14812712398392,4sleep140-21swapper/1419:06:246
14812812397390,4sleep70-21swapper/719:06:3213
14813262396390,4sleep130-21swapper/1319:07:115
14813182395389,4sleep50-21swapper/519:07:0211
14813512394387,4sleep40-21swapper/419:07:3310
14787712392386,4sleep10-21swapper/119:05:061
148184199290,27cyclictest0-21swapper/1019:45:132
148181199290,1cyclictest0-21swapper/100:34:341
1481856992827,1cyclictest1005269-21snmpd00:19:107
148185699280,27cyclictest0-21swapper/1521:51:337
1481854992826,1cyclictest1005269-21snmpd23:36:576
148185499280,27cyclictest0-21swapper/1420:55:106
1481850992827,1cyclictest1005269-21snmpd22:00:455
148184899286,22cyclictest0-21swapper/1223:26:544
148184899280,27cyclictest0-21swapper/1222:32:564
148184899280,27cyclictest0-21swapper/1219:33:234
148184499280,27cyclictest0-21swapper/1122:34:233
148184199280,27cyclictest0-21swapper/1021:44:492
1481838992827,1cyclictest1005269-21snmpd20:14:4515
148183899280,27cyclictest0-21swapper/923:59:4615
148183899280,27cyclictest0-21swapper/923:34:5515
148183899280,27cyclictest0-21swapper/922:26:2515
148183899280,27cyclictest0-21swapper/922:22:2615
148183899280,27cyclictest0-21swapper/921:30:2615
148183899280,27cyclictest0-21swapper/900:35:1615
1481833992827,1cyclictest1005269-21snmpd23:06:4213
148182899280,27cyclictest0-21swapper/623:38:4212
148182899280,27cyclictest0-21swapper/619:24:2012
148182899280,27cyclictest0-21swapper/600:28:5012
148182099280,27cyclictest0-21swapper/423:18:2010
148182099280,27cyclictest0-21swapper/422:41:3210
148181599280,27cyclictest0-21swapper/321:53:499
148181599280,27cyclictest0-21swapper/321:30:139
1481811992827,1cyclictest1005269-21snmpd23:59:361
1481811992825,1cyclictest1005269-21snmpd23:51:071
1481856992726,1cyclictest1005269-21snmpd23:10:277
148185699270,27cyclictest0-21swapper/1521:08:537
148185699270,1cyclictest0-21swapper/1522:06:337
1481854992726,1cyclictest1005269-21snmpd19:21:356
1481854992725,2cyclictest1005269-21snmpd22:30:496
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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