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2024-12-10 - 21:40
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot6.osadl.org (updated Tue Dec 10, 2024 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
593519956132,29cyclictest0-21swapper/1523:32:447
59319995548,44cyclictest0-21swapper/721:09:4313
593519954011,29cyclictest0-21swapper/1523:03:457
593199953841,497cyclictest0-21swapper/722:06:4313
593479953335,0cyclictest0-21swapper/1420:52:436
593519953130,500cyclictest0-21swapper/1500:05:207
593199952627,499cyclictest0-21swapper/700:14:4313
593519952523,501cyclictest0-21swapper/1520:53:557
593419952310,43cyclictest0-21swapper/1221:33:204
593419952310,43cyclictest0-21swapper/1221:33:204
593199951949,470cyclictest0-21swapper/721:58:3313
593519951816,499cyclictest0-21swapper/1523:10:217
593199951721,29cyclictest0-21swapper/721:18:2213
593479951615,500cyclictest0-21swapper/1422:43:456
593199951618,0cyclictest0-21swapper/719:15:4513
59351995132,44cyclictest0-21swapper/1520:59:437
593519951312,498cyclictest0-21swapper/1523:44:417
593519949961,437cyclictest0-21swapper/1520:23:437
5935199499498,0cyclictest188830-21kworker/15:2+i915-unordered22:52:217
593199949929,0cyclictest0-21swapper/700:22:5913
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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