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2025-07-12 - 12:53

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot6s.osadl.org (updated Sat Jul 12, 2025 00:46:06)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
3576584991209,53cyclictest0-21swapper/721:45:0217
3576601998425,58cyclictest0-21swapper/1320:36:455
38866132830,0sleep12265-21kswapd000:22:334
38517982740,0sleep170-21swapper/1723:45:559
3576601997412,61cyclictest0-21swapper/1323:19:225
3576601997412,61cyclictest0-21swapper/1323:19:225
58366620690,1data-loop.00-21swapper/1521:59:047
3576601996817,50cyclictest0-21swapper/1320:45:595
3576574996817,50cyclictest0-21swapper/320:05:2113
3576574996516,48cyclictest0-21swapper/321:11:0613
357657499643,60cyclictest0-21swapper/319:27:0513
3576566996317,45cyclictest3842516-40tracker-miner-f23:40:030
3576601996130,31cyclictest115050irq/18-parport021:24:505
3576574996020,39cyclictest0-21swapper/300:35:5913
3576601995927,32cyclictest0-21swapper/1320:55:335
3576601995927,32cyclictest0-21swapper/1320:55:335
37786882580,0sleep180-21swapper/1822:34:0910
3576601995816,41cyclictest0-21swapper/1321:39:585
3576574995832,25cyclictest0-21swapper/320:33:4713
3576568995831,0cyclictest0-21swapper/122:59:411
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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