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2024-05-21 - 19:05

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #6

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Note that this system runs a non-RT kernel.
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack0slot6s.osadl.org (updated Tue May 21, 2024 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
36745739990539051,2cyclictest16-1pr/ttyS000:00:1610
36745759990529047,5cyclictest16-1pr/ttyS023:30:1811
36745739990529050,2cyclictest16-1pr/ttyS022:25:1810
36745409990479043,4cyclictest16-1pr/ttyS019:54:5818
36745569990469044,2cyclictest16-1pr/ttyS021:05:135
36745409990469044,2cyclictest16-1pr/ttyS019:44:5618
36745409990459039,6cyclictest16-1pr/ttyS021:50:2018
36745409990429038,4cyclictest16-1pr/ttyS019:55:1418
36745759990419039,2cyclictest16-1pr/ttyS023:50:1411
36745759990369034,2cyclictest16-1pr/ttyS023:40:1411
36745739990369032,4cyclictest16-1pr/ttyS000:25:5010
36745569990369032,4cyclictest16-1pr/ttyS020:45:175
36745409990369035,1cyclictest16-1pr/ttyS019:35:1618
36745409990369033,3cyclictest16-1pr/ttyS022:10:1218
36745569990359033,2cyclictest16-1pr/ttyS021:00:125
36745409990349032,2cyclictest16-1pr/ttyS020:15:1418
36745409990339030,3cyclictest16-1pr/ttyS020:07:0118
36745409990329031,1cyclictest16-1pr/ttyS000:10:1218
36745409990329031,1cyclictest16-1pr/ttyS000:10:1218
36745409990329030,2cyclictest16-1pr/ttyS021:25:1618
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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