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2024-07-27 - 03:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot6.osadl.org (updated Sat Jul 27, 2024 00:46:43)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
56918099733732,1cyclictest0-21swapper/1200:26:434
5691559958232,45cyclictest0-21swapper/521:50:2211
5691619957322,45cyclictest0-21swapper/700:14:4413
569161995708,45cyclictest0-21swapper/723:57:5813
5691559957030,29cyclictest0-21swapper/519:14:4411
5691619956413,29cyclictest0-21swapper/719:40:4513
5691519955620,45cyclictest0-21swapper/419:49:2010
5691719955418,45cyclictest0-21swapper/1022:23:582
569190995479,536cyclictest0-21swapper/1521:13:197
5691769954524,0cyclictest0-21swapper/1123:40:553
5691619954120,519cyclictest0-21swapper/721:35:5213
5691519954017,521cyclictest0-21swapper/422:23:4310
569161995385,43cyclictest0-21swapper/719:31:4313
5691619953110,521cyclictest0-21swapper/723:54:4313
5691519952837,490cyclictest0-21swapper/423:07:4510
569161995273,521cyclictest0-21swapper/700:08:2313
5691379952628,498cyclictest0-21swapper/020:42:450
569161995256,519cyclictest0-21swapper/720:35:2213
5691619952543,0cyclictest0-21swapper/720:40:2213
56914799522515,4cyclictest480075-21kworker/3:0+events23:40:559
56914599520518,2cyclictest720960-21kworker/2:2+i915-unordered22:24:228
5691419952014,506cyclictest0-21swapper/122:51:221
569161995190,0cyclictest0-21swapper/720:46:4613
56915199517516,1cyclictest0-21swapper/419:53:5810
56914599517486,31cyclictest0-21swapper/222:40:228
56914599517486,31cyclictest0-21swapper/222:40:228
56916599514514,0cyclictest732440-21kworker/8:2+i915-unordered22:43:2114
56916599514514,0cyclictest732440-21kworker/8:2+i915-unordered22:43:2114
56919099513513,0cyclictest701586-21kworker/15:2+i915-unordered21:59:217
56918599513511,2cyclictest817837-21kworker/13:1+i915-unordered00:29:415
56918599507507,0cyclictest697523-21kworker/13:1+i915-unordered22:11:595
569161995069,497cyclictest0-21swapper/721:03:5913
5691579950241,461cyclictest0-21swapper/600:09:4312
56917699499499,0cyclictest597031-21kworker/11:2+events21:22:433
569185994987,490cyclictest0-21swapper/1319:33:435
5691579949819,476cyclictest0-21swapper/600:21:4212
56914799498469,29cyclictest0-21swapper/321:20:599
569190994965,491cyclictest0-21swapper/1523:16:227
56916199496495,1cyclictest0-21swapper/700:21:4213
5691579949316,476cyclictest0-21swapper/620:52:2012
569151994910,490cyclictest0-21swapper/420:27:4610
56914599490461,29cyclictest0-21swapper/223:25:598
5691579948912,475cyclictest0-21swapper/619:23:4312
5691519948936,453cyclictest0-21swapper/419:11:4210
56919099488458,30cyclictest0-21swapper/1520:35:597
5691579948813,475cyclictest0-21swapper/622:12:2112
56916599487486,1cyclictest0-21swapper/823:12:2214
56915599487486,1cyclictest585220-21kworker/5:1+i915-unordered19:33:4211
56916199486457,29cyclictest0-21swapper/700:16:4413
5691579948623,461cyclictest0-21swapper/622:43:2212
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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