You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-04-19 - 23:42

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #0, slot #7

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot7s.osadl.org (updated Fri Apr 19, 2024 00:43:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2407754211970,20sleep00-21swapper/019:05:550
2407857211369,19sleep10-21swapper/119:07:121
2408039210960,41sleep30-21swapper/319:09:313
2407802210577,20sleep20-21swapper/219:06:332
240821699280,4cyclictest0-21swapper/300:18:393
2408216992712,15cyclictest0-21swapper/320:15:203
2408214992612,13cyclictest0-21swapper/220:15:112
2408210992612,13cyclictest0-21swapper/120:15:161
240821099260,25cyclictest0-21swapper/100:27:091
240820899260,2cyclictest0-21swapper/023:08:510
240820899260,25cyclictest0-21swapper/019:56:460
2408214992512,10cyclictest2451556-21ntpq20:55:172
2408210992511,13cyclictest0-21swapper/120:55:081
240821699230,15cyclictest0-21swapper/300:24:093
2408216992112,8cyclictest0-21swapper/319:56:253
2408208992111,9cyclictest0-21swapper/022:50:000
2408216992010,4cyclictest0-21swapper/323:33:293
240821699200,19cyclictest0-21swapper/320:42:053
2408214992011,9cyclictest0-21swapper/200:17:582
2408210992012,8cyclictest0-21swapper/100:37:181
240821699190,19cyclictest0-21swapper/323:50:203
240821699190,18cyclictest2472795-21cat21:50:103
240821099190,4cyclictest0-21swapper/120:25:471
240820899199,5cyclictest0-21swapper/020:52:430
240821699180,3cyclictest0-21swapper/323:36:343
240821699180,3cyclictest0-21swapper/300:08:333
240821499188,10cyclictest0-21swapper/222:18:052
2408214991814,4cyclictest0-21swapper/222:40:152
240821099184,13cyclictest0-21swapper/123:25:341
240821099180,3cyclictest0-21swapper/121:17:231
240821099180,3cyclictest0-21swapper/119:53:371
240821099180,2cyclictest2481400-21ntpq22:10:161
240820899188,4cyclictest0-21swapper/023:47:140
2408208991815,2cyclictest1026-21snmpd20:33:350
2408208991814,4cyclictest0-21swapper/020:57:540
240820899180,6cyclictest0-21swapper/022:40:180
240820899180,16cyclictest0-21swapper/019:45:150
240821699177,1cyclictest0-21swapper/323:08:193
240821699170,6cyclictest0-21swapper/321:48:223
240821699170,2cyclictest0-21swapper/319:50:143
240821699170,17cyclictest0-21swapper/319:19:443
240821699170,16cyclictest0-21swapper/322:36:023
240821699170,15cyclictest0-21swapper/320:09:343
240821099178,9cyclictest0-21swapper/121:45:551
2408210991715,1cyclictest1026-21snmpd22:16:081
2408210991715,1cyclictest1026-21snmpd00:21:331
240821099170,17cyclictest0-21swapper/122:08:471
240821099170,16cyclictest0-21swapper/123:52:591
240821099170,16cyclictest0-21swapper/120:30:051
240821099170,16cyclictest0-21swapper/100:10:301
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional