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2024-09-16 - 06:05

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack0slot8s.osadl.org (updated Mon Sep 16, 2024 00:44:46)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
89229484,8sleep110-21swapper/1119:06:123
275991900,81ptp4l0-21swapper/119:06:171
115626756,9sleep50-21swapper/519:09:187
53426653,10sleep00-21swapper/019:05:250
3262526451,10sleep100-21swapper/1019:05:232
93726250,9sleep60-21swapper/619:06:318
83526251,9sleep40-21swapper/419:05:296
83826150,9sleep70-21swapper/719:05:329
44472500,0sleep70-21swapper/721:15:209
159272490,0sleep50-21swapper/522:15:137
162182460,0sleep863-21ksoftirqd/822:55:2010
32822430,0sleep50-21swapper/500:05:007
160099234,12cyclictest0-21swapper/222:10:014
94980220,2rtkit-daemon0-21swapper/319:08:115
160599202,13cyclictest0-21swapper/322:05:015
160099203,10cyclictest0-21swapper/223:50:004
165699190,4cyclictest0-21swapper/1100:30:183
163899183,8cyclictest0-21swapper/821:20:0110
163499185,8cyclictest0-21swapper/722:40:019
163499180,17cyclictest0-21swapper/722:10:079
160999180,14cyclictest0-21swapper/400:30:006
160099183,9cyclictest0-21swapper/223:50:004
160099183,10cyclictest0-21swapper/221:55:014
160099183,10cyclictest0-21swapper/219:10:004
164799170,1cyclictest0-21swapper/1000:40:002
164399173,8cyclictest0-21swapper/923:30:0111
164399173,8cyclictest0-21swapper/920:45:0011
164399173,8cyclictest0-21swapper/920:45:0011
164399173,8cyclictest0-21swapper/900:10:0011
1634991716,1cyclictest0-21swapper/723:29:569
163499170,3cyclictest0-21swapper/721:05:189
160599173,9cyclictest0-21swapper/320:00:015
160599172,9cyclictest0-21swapper/300:05:005
160099173,10cyclictest0-21swapper/222:50:014
324692167,7sleep80-21swapper/819:05:2110
275991160,1ptp4l0-21swapper/123:45:241
165699161,9cyclictest0-21swapper/1120:25:003
163499163,7cyclictest0-21swapper/721:00:019
160099163,8cyclictest0-21swapper/221:05:014
160099163,8cyclictest0-21swapper/219:25:004
160099162,10cyclictest0-21swapper/222:00:014
159699160,1cyclictest29731-21awk00:40:001
19342150,0sleep00-21swapper/021:55:180
164399152,7cyclictest0-21swapper/923:00:0111
164399152,7cyclictest0-21swapper/919:45:0111
163899152,8cyclictest0-21swapper/820:35:0110
163499153,7cyclictest0-21swapper/700:35:009
163499152,8cyclictest0-21swapper/723:00:019
163499152,7cyclictest0-21swapper/722:05:019
160099159,5cyclictest8046-21cpuspeed_turbos20:40:124
160099159,5cyclictest8046-21cpuspeed_turbos20:40:124
160099153,8cyclictest0-21swapper/222:20:014
160099153,8cyclictest0-21swapper/220:00:004
160099153,7cyclictest0-21swapper/223:45:004
160099153,7cyclictest0-21swapper/220:10:004
160099152,9cyclictest0-21swapper/200:30:004
160099152,8cyclictest0-21swapper/223:30:014
160099152,8cyclictest0-21swapper/200:10:264
160099151,9cyclictest0-21swapper/220:20:004
160099150,14cyclictest20170-21taskset20:55:144
160099150,14cyclictest12217-21expr20:45:124
160099150,14cyclictest12217-21expr20:45:124
160099150,14cyclictest0-21swapper/223:10:164
160099150,14cyclictest0-21swapper/200:35:264
160099150,14cyclictest0-21swapper/200:30:214
159699153,7cyclictest0-21swapper/121:50:011
159699153,7cyclictest0-21swapper/100:20:001
159699150,9cyclictest0-21swapper/119:40:001
275991140,1ptp4l21-21ksoftirqd/122:31:501
275991140,1ptp4l21-21ksoftirqd/121:35:181
275991140,0ptp4l0-21swapper/123:55:181
275991140,0ptp4l0-21swapper/122:25:161
275991140,0ptp4l0-21swapper/121:50:231
275991140,0ptp4l0-21swapper/100:05:151
165699143,6cyclictest0-21swapper/1121:50:013
165699142,6cyclictest0-21swapper/1123:10:013
164399143,7cyclictest0-21swapper/921:05:0111
164399142,7cyclictest0-21swapper/921:40:0111
163899142,7cyclictest0-21swapper/821:25:0110
163899142,7cyclictest0-21swapper/820:45:2310
163899142,7cyclictest0-21swapper/820:45:2310
163499144,6cyclictest14443-21kworker/u24:022:45:019
162599142,7cyclictest0-21swapper/523:05:017
160099142,8cyclictest0-21swapper/222:30:014
160099142,7cyclictest0-21swapper/219:10:234
160099140,13cyclictest0-21swapper/223:33:244
160099140,13cyclictest0-21swapper/221:15:144
160099140,13cyclictest0-21swapper/221:12:534
160099140,13cyclictest0-21swapper/220:25:164
160099140,13cyclictest0-21swapper/220:25:164
160099140,13cyclictest0-21swapper/220:12:574
160099140,13cyclictest0-21swapper/219:50:214
159699143,8cyclictest0-21swapper/100:25:001
159199143,8cyclictest0-21swapper/019:50:010
159199142,9cyclictest0-21swapper/022:15:010
275991130,5ptp4l21-21ksoftirqd/121:00:151
275991130,1ptp4l21-21ksoftirqd/121:30:211
275991130,1ptp4l21-21ksoftirqd/120:31:591
275991130,0ptp4l0-21swapper/121:40:131
165699132,7cyclictest0-21swapper/1123:11:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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