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2026-02-13 - 02:30
[ 290.152] (II) VESA: driver for VESA chipsets: vesa

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Fri Feb 13, 2026 00:44:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
94080920,87rtkit-daemon0-21swapper/419:07:026
94080920,87rtkit-daemon0-21swapper/419:07:026
283491820,65ptp4l0-21swapper/119:05:341
283491820,65ptp4l0-21swapper/119:05:341
2567627158,10sleep110-21swapper/1119:05:153
2567627158,10sleep110-21swapper/1119:05:153
2813826952,9sleep50-21swapper/519:09:457
2813826952,9sleep50-21swapper/519:09:447
2804026756,9sleep00-21swapper/019:08:160
2804026756,9sleep00-21swapper/019:08:160
2808926653,11sleep100-21swapper/1019:09:022
2808926653,11sleep100-21swapper/1019:09:022
2805926655,9sleep60-21swapper/619:08:338
2805926655,9sleep60-21swapper/619:08:338
2793426654,10sleep70-21swapper/719:06:479
2793426654,10sleep70-21swapper/719:06:469
46522520,0sleep100-21swapper/1022:50:002
2850299243,8cyclictest0-21swapper/400:40:006
2850299212,15cyclictest0-21swapper/421:55:016
2850299212,15cyclictest0-21swapper/419:45:006
2850299212,14cyclictest0-21swapper/421:40:016
2850299211,7cyclictest0-21swapper/422:05:016
2852599193,11cyclictest0-21swapper/900:40:0011
2849799193,9cyclictest0-21swapper/319:55:015
2849399194,9cyclictest0-21swapper/219:15:014
2849399194,9cyclictest0-21swapper/219:15:004
2851599183,9cyclictest0-21swapper/719:25:019
2851599183,9cyclictest0-21swapper/719:25:019
2851599181,2cyclictest0-21swapper/721:25:179
2851199182,10cyclictest0-21swapper/623:30:008
2849399183,10cyclictest0-21swapper/222:20:014
2848099183,9cyclictest0-21swapper/023:00:000
106482180,0sleep50-21swapper/521:30:237
2852599173,10cyclictest0-21swapper/923:20:0011
28511991715,1cyclictest0-21swapper/621:30:018
2849799172,8cyclictest0-21swapper/322:30:005
2849799172,8cyclictest0-21swapper/320:35:015
2849399174,8cyclictest0-21swapper/222:30:004
2849399173,9cyclictest0-21swapper/223:20:004
2849399173,8cyclictest0-21swapper/221:30:244
2849399173,8cyclictest0-21swapper/220:50:014
2848799172,10cyclictest0-21swapper/122:05:011
283491170,1ptp4l21-21ksoftirqd/123:40:151
280482178,7sleep80-21swapper/819:08:2410
280482178,7sleep80-21swapper/819:08:2410
2853599162,9cyclictest0-21swapper/1120:05:013
28515991613,2cyclictest0-21swapper/722:05:169
2851199164,7cyclictest0-21swapper/620:45:248
2851199164,7cyclictest0-21swapper/620:45:018
2849399163,8cyclictest0-21swapper/222:15:004
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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