You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2024-07-27 - 07:16

OSADL QA Farm on Real-time of Mainline Linux

About - Hardware - CPUs - Benchmarks - Graphics - Benchmarks - Kernels - Boards/Distros - Latency monitoring - Latency plots - System data - Profiles - Compare - Awards

Default latency plot of shadow in rack #0, slot #8

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
Special  All - All RT - Optimization - Ethernet - Thumbnails - Next
  
Click here to display the system's profile data or here to proceed to next system.
Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack0slot8s.osadl.org (updated Sat Jul 27, 2024 00:44:52)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
288991870,75ptp4l0-21swapper/119:05:121
94480860,80rtkit-daemon0-21swapper/519:05:047
2485426353,8sleep40-21swapper/419:09:106
2460926251,9sleep00-21swapper/019:05:280
2490326049,9sleep110-21swapper/1119:09:533
2488525745,10sleep70-21swapper/719:09:369
2163425746,9sleep60-21swapper/619:05:118
2465925544,9sleep100-21swapper/1019:06:152
121202460,0sleep50-21swapper/519:30:247
288991200,1ptp4l21-21ksoftirqd/123:55:021
94480190,5rtkit-daemon0-21swapper/521:50:007
2530899194,9cyclictest0-21swapper/922:00:0011
25272991916,2cyclictest23389-21turbostat21:55:011
288991180,1ptp4l21-21ksoftirqd/100:20:231
25308991816,1cyclictest0-21swapper/921:10:0111
2529599180,2cyclictest0-21swapper/623:10:178
2529099181,16cyclictest0-21swapper/519:25:207
25308991714,2cyclictest8655-21turbostat23:00:0011
2529999173,8cyclictest0-21swapper/720:50:019
2529999173,8cyclictest0-21swapper/720:50:009
2529999172,9cyclictest0-21swapper/722:25:319
248452178,7sleep80-21swapper/819:09:0110
288991160,1ptp4l21-21ksoftirqd/122:40:191
288991160,1ptp4l21-21ksoftirqd/121:40:101
288991160,1ptp4l21-21ksoftirqd/121:15:111
288991160,0ptp4l0-21swapper/123:15:271
288991160,0ptp4l0-21swapper/120:40:141
288991160,0ptp4l0-21swapper/120:40:131
288991160,0ptp4l0-21swapper/120:05:191
2530899163,8cyclictest0-21swapper/900:15:0011
2530899162,8cyclictest0-21swapper/900:09:5911
2530899162,7cyclictest0-21swapper/922:50:0111
25290991612,3cyclictest0-21swapper/521:10:177
2528199163,8cyclictest0-21swapper/322:55:005
2528199162,8cyclictest0-21swapper/320:10:015
2528199162,11cyclictest14366-21kworker/u24:223:50:005
2526899163,8cyclictest0-21swapper/019:20:010
2526899162,8cyclictest0-21swapper/019:35:010
288991150,1ptp4l21-21ksoftirqd/122:00:111
288991150,1ptp4l21-21ksoftirqd/121:45:231
288991150,1ptp4l21-21ksoftirqd/121:05:121
288991150,1ptp4l21-21ksoftirqd/120:01:011
288991150,1ptp4l21-21ksoftirqd/119:25:121
288991150,0ptp4l0-21swapper/121:55:191
288991150,0ptp4l0-21swapper/119:35:151
288991150,0ptp4l0-21swapper/100:30:111
2530899153,7cyclictest0-21swapper/919:40:0111
2530899152,8cyclictest0-21swapper/922:55:0111
2530899152,7cyclictest0-21swapper/921:40:0011
2529599153,7cyclictest0-21swapper/621:50:018
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional