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2019-07-17 - 00:29

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.19.8-rt6 (Profile)

Latency plot of system in rack #1, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot0.osadl.org (updated Tue Jul 16, 2019 12:44:04)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2817825836,7sleep00-21swapper/007:07:420
2824925332,7sleep10-21swapper/107:08:311
2805125140,7sleep30-21swapper/307:06:083
2820724926,7sleep20-21swapper/207:08:042
94022160,1sleep29405-21nfsd409:00:062
28566991414,0cyclictest2233-40kipmi012:10:050
2858599129,2cyclictest0-21swapper/208:55:042
2858599127,1cyclictest0-21swapper/210:45:112
28566991111,0cyclictest2233-40kipmi011:25:090
2859199100,9cyclictest0-21swapper/308:38:453
2858599107,0cyclictest0-21swapper/212:15:072
2856699109,0cyclictest32739-21kworker/0:008:50:060
285919998,0cyclictest0-21swapper/312:00:443
285919998,0cyclictest0-21swapper/311:42:483
285919998,0cyclictest0-21swapper/311:06:093
285919998,0cyclictest0-21swapper/310:09:103
285919998,0cyclictest0-21swapper/309:40:163
285919998,0cyclictest0-21swapper/308:52:093
285919990,0cyclictest0-21swapper/311:59:363
285919990,0cyclictest0-21swapper/310:55:203
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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