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2025-07-07 - 02:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Mon Jul 07, 2025 00:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
203192232159,26sleep20-21swapper/219:07:032
204962222147,24sleep00-21swapper/019:09:220
204922198157,27sleep10-21swapper/119:09:191
204242198161,24sleep30-21swapper/319:08:243
110522730,0sleep00-21swapper/000:39:030
272652710,0sleep20-21swapper/200:17:112
199142180,0sleep20-21swapper/200:07:372
33322160,0sleep00-21swapper/022:20:130
2064099140,1cyclictest0-21swapper/121:50:231
2063399143,5cyclictest26862-21cat20:30:000
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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