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2025-04-18 - 19:30
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot1.osadl.org (updated Fri Apr 18, 2025 12:45:17)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
83782213154,47sleep30-21swapper/307:08:153
83872203163,26sleep20-21swapper/207:08:222
82572203165,25sleep10-21swapper/107:06:411
83132198159,26sleep00-21swapper/007:07:240
19132670,0sleep20-21swapper/209:10:172
16312610,0sleep20-21swapper/211:20:432
79622150,0sleep20-21swapper/212:18:212
8585991311,1cyclictest9-21ksoftirqd/010:35:000
858599130,10cyclictest17100-1kworker/u9:011:00:140
858599130,10cyclictest17100-1kworker/u9:011:00:140
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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