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2023-04-01 - 16:37

x86 Intel Core i5-7300U @2600 MHz, Linux 5.0.21-rt16 (Profile)

Latency plot of system in rack #1, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, highest latencies:
System rack1slot1.osadl.org (updated Sat Apr 01, 2023 12:44:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
215572780,0sleep10-21swapper/112:20:321
321523331,1sleep10-21swapper/107:07:301
3521992214,7cyclictest7127-21fschecks_count09:30:170
3521992114,6cyclictest793-21snmpd12:24:260
3521992013,6cyclictest0-21swapper/012:38:470
354199195,13cyclictest72150irq/122-eno110:19:302
353399190,18cyclictest0-21swapper/109:40:181
3521991913,6cyclictest0-21swapper/011:20:270
3521991812,5cyclictest0-21swapper/009:26:210
3521991812,5cyclictest0-21swapper/008:08:010
3521991812,1cyclictest818-21lldpd10:25:560
3521991812,1cyclictest818-21lldpd10:25:560
3521991812,0cyclictest0-21swapper/010:54:480
3521991811,6cyclictest23821-21diskmemload12:12:050
354199173,13cyclictest72150irq/122-eno112:05:302
354199173,13cyclictest72150irq/122-eno111:59:132
354199170,1cyclictest15003-21latency_hist09:40:002
353399170,13cyclictest0-21swapper/110:54:341
353399170,1cyclictest0-21swapper/110:33:121
3521991712,4cyclictest818-21lldpd10:36:190
3521991710,6cyclictest793-21snmpd10:34:010
3521991710,6cyclictest793-21snmpd09:51:390
3521991710,6cyclictest23821-21diskmemload09:20:500
352199170,16cyclictest0-21swapper/009:13:160
352199170,1cyclictest793-21snmpd09:42:000
3545991616,0cyclictest793-21snmpd11:14:243
3545991615,1cyclictest793-21snmpd11:09:563
3545991614,1cyclictest32593-21cstates12:35:213
354599160,0cyclictest0-21swapper/309:36:293
3541991616,0cyclictest72150irq/122-eno107:21:492
3541991615,0cyclictest72150irq/122-eno111:05:342
3541991612,3cyclictest0-21swapper/210:52:482
354199160,13cyclictest0-21swapper/210:11:362
3533991612,4cyclictest0-21swapper/109:53:361
3533991611,4cyclictest0-21swapper/112:30:151
353399160,16cyclictest0-21swapper/107:12:371
353399160,1cyclictest0-21swapper/111:37:491
353399160,0cyclictest0-21swapper/112:19:331
3521991616,0cyclictest0-21swapper/007:41:560
3521991615,1cyclictest793-21snmpd07:22:050
3521991610,5cyclictest0-21swapper/012:07:470
352199161,14cyclictest818-21lldpd10:40:230
106392160,1sleep0793-21snmpd11:30:190
3545991515,0cyclictest23821-21diskmemload10:34:053
3545991515,0cyclictest23821-21diskmemload10:04:163
3545991513,1cyclictest793-21snmpd11:44:433
3545991513,1cyclictest793-21snmpd10:38:133
354599150,14cyclictest16261-21ntp_states08:50:293
354199152,0cyclictest72150irq/122-eno112:12:052
3541991514,1cyclictest271rcuc/210:43:452
3541991513,1cyclictest72150irq/122-eno110:46:032
3541991513,1cyclictest0-21swapper/210:38:022
3541991513,1cyclictest0-21swapper/210:25:162
3541991513,1cyclictest0-21swapper/210:25:162
3541991512,2cyclictest818-21lldpd12:30:292
3541991512,2cyclictest793-21snmpd07:19:072
3541991512,2cyclictest23821-21diskmemload11:52:492
3541991512,2cyclictest23821-21diskmemload11:26:502
3541991512,2cyclictest23821-21diskmemload09:12:242
3541991512,2cyclictest0-21swapper/211:20:212
3541991511,3cyclictest0-21swapper/209:22:222
354199151,13cyclictest818-21lldpd09:18:182
354199151,13cyclictest25939-21ssh11:48:292
354199151,13cyclictest0-21swapper/211:03:242
354199151,1cyclictest0-21swapper/211:17:542
354199150,14cyclictest818-21lldpd09:34:032
354199150,14cyclictest818-21lldpd08:55:282
354199150,14cyclictest793-21snmpd10:33:202
354199150,14cyclictest793-21snmpd09:03:092
354199150,14cyclictest23821-21diskmemload12:36:332
354199150,13cyclictest0-21swapper/212:15:372
3533991512,3cyclictest0-21swapper/112:09:301
3533991512,3cyclictest0-21swapper/110:03:091
3533991512,3cyclictest0-21swapper/109:04:351
3533991512,2cyclictest0-21swapper/111:28:581
3533991511,4cyclictest0-21swapper/109:23:471
353399151,13cyclictest0-21swapper/111:54:571
353399150,0cyclictest0-21swapper/107:34:541
352199151,13cyclictest818-21lldpd12:26:400
352199151,13cyclictest818-21lldpd11:13:470
352199151,13cyclictest793-21snmpd07:55:210
352199151,13cyclictest0-21swapper/010:55:250
352199151,1cyclictest818-21lldpd10:17:400
352199151,1cyclictest0-21swapper/010:46:300
352199151,1cyclictest0-21swapper/010:20:030
3545991413,1cyclictest818-21lldpd08:19:403
3545991413,1cyclictest818-21lldpd08:19:393
3545991413,1cyclictest0-21swapper/311:36:063
3545991412,1cyclictest818-21lldpd10:44:313
3545991412,1cyclictest818-21lldpd10:07:533
3545991412,1cyclictest818-21lldpd09:05:293
3545991412,1cyclictest818-21lldpd09:03:193
3545991412,1cyclictest19126-21sh10:21:563
354599141,1cyclictest0-21swapper/312:26:573
354599140,13cyclictest818-21lldpd12:06:073
354599140,13cyclictest818-21lldpd11:01:373
354599140,13cyclictest818-21lldpd10:10:173
354599140,13cyclictest818-21lldpd09:30:243
354599140,13cyclictest818-21lldpd09:20:333
354599140,13cyclictest793-21snmpd12:16:303
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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