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2024-07-27 - 08:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Sat Jul 27, 2024 00:45:05)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
223542210155,44sleep10-21swapper/119:07:351
225192203161,28sleep20-21swapper/219:09:442
224062202164,25sleep30-21swapper/319:08:173
222642199161,25sleep00-21swapper/019:06:240
296632620,0sleep2271rcuc/220:30:132
243852610,0sleep00-21swapper/023:40:160
232162170,0sleep20-21swapper/222:05:292
2263199150,14cyclictest5369-21ntp_states21:40:192
2263199150,14cyclictest30512-21irqstats00:35:152
2263199150,14cyclictest0-21swapper/200:25:132
2263199140,13cyclictest30382-21perf19:25:012
2263199140,13cyclictest12903-21users21:50:272
2263199140,13cyclictest0-21swapper/223:26:202
2263199140,13cyclictest0-21swapper/223:00:242
2263199140,0cyclictest25377-21munin-node19:15:002
2263199134,8cyclictest15452-21diskmemload21:25:332
2263199130,12cyclictest4881-21aten_r1power_en00:00:112
2263199130,12cyclictest0-21swapper/220:10:142
2263199130,12cyclictest0-21swapper/200:00:002
2263199130,1cyclictest0-21swapper/222:55:172
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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