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2025-07-12 - 11:09
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Sat Jul 12, 2025 00:45:12)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
31102210156,42sleep00-21swapper/019:09:180
28302202164,25sleep30-21swapper/319:05:383
31172201162,26sleep20-21swapper/219:09:242
28682199160,26sleep10-21swapper/119:06:091
218572700,0sleep10-21swapper/123:10:001
316742650,0sleep00-21swapper/021:13:360
3270992323,0cyclictest28-21ksoftirqd/221:24:492
3270991817,1cyclictest28-21ksoftirqd/220:40:162
3270991817,1cyclictest28-21ksoftirqd/219:55:162
3270991717,0cyclictest28-21ksoftirqd/221:45:142
3270991716,1cyclictest28-21ksoftirqd/222:10:172
3270991716,1cyclictest28-21ksoftirqd/200:05:142
3270991716,0cyclictest28-21ksoftirqd/222:45:152
3270991616,0cyclictest28-21ksoftirqd/223:08:512
3270991616,0cyclictest28-21ksoftirqd/221:32:012
3270991616,0cyclictest28-21ksoftirqd/221:29:042
3270991616,0cyclictest28-21ksoftirqd/200:22:152
3270991615,1cyclictest28-21ksoftirqd/221:14:562
3270991615,1cyclictest28-21ksoftirqd/219:50:212
3270991615,1cyclictest28-21ksoftirqd/200:29:512
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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