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2026-07-11 - 00:57
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot1.osadl.org (updated Fri Jul 10, 2026 12:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
136662214148,52sleep00-21swapper/007:07:000
137962209157,25sleep30-21swapper/307:08:403
137802200163,25sleep20-21swapper/207:08:272
136572196159,24sleep10-21swapper/107:06:531
237112720,1sleep023716-21gltestperf08:35:150
303742580,0sleep00-21swapper/008:50:130
172742340,0sleep36841-21diskmemload10:50:153
104502220,0sleep00-21swapper/009:15:010
112652190,0sleep10-21swapper/109:58:421
14011991313,0cyclictest35-21ksoftirqd/309:25:203
1399299132,5cyclictest22005-21latency_hist09:30:010
14011991210,1cyclictest35-21ksoftirqd/311:29:593
1401199120,9cyclictest240-21systemd-journal11:58:013
1399299120,6cyclictest0-21swapper/007:10:110
170322110,0sleep10-21swapper/109:22:091
1401199119,1cyclictest35-21ksoftirqd/312:15:003
1401199119,1cyclictest35-21ksoftirqd/310:45:183
14011991111,0cyclictest35-21ksoftirqd/311:45:123
14011991110,1cyclictest35-21ksoftirqd/310:10:123
14011991110,1cyclictest35-21ksoftirqd/309:20:113
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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