You are here: Home / Projects / OSADL QA Farm Real-time / Latency plots / 
2023-06-03 - 07:50

x86 Intel Core i5-7300U @2600 MHz, Linux 5.0.21-rt16 (Profile)

Latency plot of system in rack #1, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot1.osadl.org (updated Sat Jun 03, 2023 00:45:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
182672218157,47sleep00-21swapper/019:05:280
183852213149,21sleep20-21swapper/219:06:592
184062198162,23sleep30-21swapper/319:07:173
184092197161,23sleep10-21swapper/119:07:191
265312720,0sleep10-21swapper/100:17:441
142442640,0sleep00-21swapper/022:00:000
51422610,0sleep00-21swapper/023:50:180
115222610,0sleep30-21swapper/322:35:393
47492210,1sleep10-21swapper/119:49:591
18723991211,1cyclictest72150irq/122-eno123:15:322
1872399120,12cyclictest0-21swapper/221:26:292
1872399112,3cyclictest361-21systemd-journal23:27:382
1870999111,2cyclictest636-21systemd-logind22:55:550
1872399100,4cyclictest0-21swapper/223:23:492
1871699108,1cyclictest21-21ksoftirqd/121:20:191
18716991010,0cyclictest21-21ksoftirqd/123:22:201
1870999102,4cyclictest24470-21perf20:35:000
32539290,0sleep30-21swapper/323:45:103
187319990,5cyclictest361-21systemd-journal19:40:003
187239996,2cyclictest28-21ksoftirqd/222:07:412
187239990,5cyclictest14647-21apt-get22:00:202
187169998,1cyclictest21-21ksoftirqd/123:55:331
187169998,1cyclictest21-21ksoftirqd/123:55:321
187169998,1cyclictest21-21ksoftirqd/122:20:261
187169998,1cyclictest21-21ksoftirqd/122:00:331
187169998,1cyclictest21-21ksoftirqd/120:25:191
187169998,1cyclictest21-21ksoftirqd/100:25:191
187169998,1cyclictest21-21ksoftirqd/100:25:191
187169998,1cyclictest21-21ksoftirqd/100:20:171
187169998,1cyclictest21-21ksoftirqd/100:09:591
187169997,1cyclictest21-21ksoftirqd/122:26:251
187169993,3cyclictest111rcu_preempt23:16:501
187169991,7cyclictest111rcu_preempt00:32:031
187169990,8cyclictest111rcu_preempt19:25:221
187169990,8cyclictest0-21swapper/123:28:001
187169990,8cyclictest0-21swapper/122:52:151
187169990,8cyclictest0-21swapper/122:52:141
187169990,8cyclictest0-21swapper/121:35:081
187319986,1cyclictest4162-21cat00:30:203
187319985,2cyclictest0-21swapper/322:17:503
187319983,4cyclictest7467-21diskmemload21:46:163
187319981,6cyclictest7467-21diskmemload23:16:063
187319981,4cyclictest7467-21diskmemload23:40:183
187319981,4cyclictest0-21swapper/319:45:003
187319981,3cyclictest7467-21diskmemload00:20:063
187319980,3cyclictest0-21swapper/300:10:143
187319980,1cyclictest0-21swapper/320:25:163
187239987,1cyclictest27514-21ntp_states22:15:282
187239986,1cyclictest793-21snmpd22:32:102
187239986,1cyclictest72150irq/122-eno121:55:312
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional