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2022-06-29 - 16:05

x86 Intel Core i5-7300U @2600 MHz, Linux 5.0.21-rt16 (Profile)

Latency plot of system in rack #1, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot1.osadl.org (updated Wed Jun 29, 2022 12:45:10)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1168423770,8sleep20-21swapper/207:05:212
122462220150,55sleep00-21swapper/007:09:190
121822206168,25sleep30-21swapper/307:08:293
121062205150,43sleep10-21swapper/107:07:311
278852760,0sleep20-21swapper/207:40:162
1239099682,11cyclictest361-21systemd-journal10:04:290
12397994719,14cyclictest90-21printk10:04:281
12410994040,0cyclictest14349-21kworker/2:210:04:372
1241899232,20cyclictest0-21swapper/310:04:273
12410991918,1cyclictest28-21ksoftirqd/209:20:582
12410991817,1cyclictest28-21ksoftirqd/211:23:162
12410991817,1cyclictest28-21ksoftirqd/210:40:132
12410991817,1cyclictest28-21ksoftirqd/210:35:532
12410991717,0cyclictest28-21ksoftirqd/211:43:262
12410991716,1cyclictest28-21ksoftirqd/211:25:012
12410991716,1cyclictest28-21ksoftirqd/209:49:502
12410991616,0cyclictest28-21ksoftirqd/212:39:442
12410991616,0cyclictest28-21ksoftirqd/209:44:082
12410991616,0cyclictest28-21ksoftirqd/209:30:262
12410991616,0cyclictest28-21ksoftirqd/209:27:502
12410991616,0cyclictest28-21ksoftirqd/209:27:502
12410991615,1cyclictest28-21ksoftirqd/211:34:462
12410991615,1cyclictest28-21ksoftirqd/210:16:172
12410991515,0cyclictest28-21ksoftirqd/212:27:442
12410991515,0cyclictest28-21ksoftirqd/211:52:132
12410991515,0cyclictest28-21ksoftirqd/211:36:572
12410991515,0cyclictest28-21ksoftirqd/211:16:342
12410991515,0cyclictest28-21ksoftirqd/210:54:142
1239799150,15cyclictest0-21swapper/112:20:121
1241099146,7cyclictest28-21ksoftirqd/207:45:132
12410991414,0cyclictest28-21ksoftirqd/212:31:542
12410991414,0cyclictest28-21ksoftirqd/212:15:232
12410991414,0cyclictest28-21ksoftirqd/212:07:172
12410991414,0cyclictest28-21ksoftirqd/211:45:362
12410991414,0cyclictest28-21ksoftirqd/211:14:362
12410991414,0cyclictest28-21ksoftirqd/211:14:362
12410991414,0cyclictest28-21ksoftirqd/210:30:032
12410991413,1cyclictest28-21ksoftirqd/210:55:242
12410991410,4cyclictest28-21ksoftirqd/209:15:142
1241099139,3cyclictest28-21ksoftirqd/211:04:202
12410991313,0cyclictest28-21ksoftirqd/212:22:152
12410991313,0cyclictest28-21ksoftirqd/210:06:592
12410991312,1cyclictest28-21ksoftirqd/210:24:402
12410991312,1cyclictest28-21ksoftirqd/210:14:272
12410991311,1cyclictest28-21ksoftirqd/207:40:002
1241099129,2cyclictest28-21ksoftirqd/209:55:112
1241099128,3cyclictest28-21ksoftirqd/212:10:412
1241099128,3cyclictest28-21ksoftirqd/207:15:162
12410991212,0cyclictest28-21ksoftirqd/211:05:122
12410991212,0cyclictest28-21ksoftirqd/210:45:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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