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2023-01-28 - 12:16

x86 Intel Core i5-7300U @2600 MHz, Linux 5.0.21-rt16 (Profile)

Latency plot of system in rack #1, slot #1
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot1.osadl.org (updated Sat Jan 28, 2023 00:45:24)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
245902200161,25sleep00-21swapper/019:07:280
247302199161,24sleep10-21swapper/119:09:191
247622198161,24sleep30-21swapper/319:09:443
247462185151,21sleep20-21swapper/219:09:322
234742610,0sleep20-21swapper/222:58:402
32902600,0sleep10-21swapper/122:05:121
103262590,0sleep2271rcuc/221:39:382
24886991312,1cyclictest0-21swapper/000:30:100
2491099110,1cyclictest30236-21python20:30:213
24894991111,0cyclictest0-21swapper/123:14:341
2488699110,11cyclictest0-21swapper/023:09:030
2488699110,11cyclictest0-21swapper/021:28:190
2491099100,6cyclictest13824-21memory22:15:163
2488699109,1cyclictest9-21ksoftirqd/000:35:110
2488699105,1cyclictest23356-21ntp_states20:15:180
2488699102,4cyclictest19537-21perf20:09:590
2488699100,0cyclictest0-21swapper/023:31:270
191962100,0sleep10-21swapper/122:54:391
5571290,0sleep014215-21diskmemload23:13:240
249009990,3cyclictest0-21swapper/219:15:112
248869998,1cyclictest9-21ksoftirqd/020:40:000
248869994,1cyclictest6534-21/usr/sbin/munin19:40:110
248869993,5cyclictest4111-21perf19:35:010
248869990,9cyclictest0-21swapper/000:27:270
248869990,5cyclictest17092-21ssh23:58:260
248869990,0cyclictest0-21swapper/022:35:270
3129280,1sleep10-21swapper/122:37:421
249109986,1cyclictest793-21snmpd20:23:183
249109986,1cyclictest793-21snmpd20:13:213
249109986,1cyclictest29334-21cat00:10:173
249109982,5cyclictest37692sleep321:31:543
249109981,2cyclictest0-21swapper/300:10:013
249009987,1cyclictest6027-21grep00:20:122
249009987,1cyclictest28-21ksoftirqd/222:20:142
249009987,1cyclictest28-21ksoftirqd/220:20:012
249009986,1cyclictest793-21snmpd23:50:482
249009986,1cyclictest72150irq/122-eno123:35:132
249009986,1cyclictest72150irq/122-eno123:10:502
249009986,1cyclictest72150irq/122-eno122:45:162
249009986,1cyclictest72150irq/122-eno122:40:162
249009986,1cyclictest72150irq/122-eno122:40:002
249009986,1cyclictest72150irq/122-eno122:25:132
249009986,1cyclictest72150irq/122-eno121:45:202
249009986,1cyclictest72150irq/122-eno121:40:142
249009986,1cyclictest72150irq/122-eno121:25:252
249009986,1cyclictest72150irq/122-eno121:20:132
249009986,1cyclictest72150irq/122-eno120:50:182
249009986,1cyclictest72150irq/122-eno120:05:152
249009986,1cyclictest72150irq/122-eno100:28:202
249009986,1cyclictest72150irq/122-eno100:15:142
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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