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2024-07-25 - 10:46
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Thu Jul 25, 2024 00:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
712924334,0sleep10-21swapper/118:47:211
725423626,0sleep30-21swapper/318:48:393
718023626,0sleep20-21swapper/218:47:542
698623523,0sleep00-21swapper/018:45:360
7409991010,0cyclictest30262-21awk19:04:251
329970,0watchdog/30-21swapper/300:00:463
29925070,0irq/32-eth0-rx-9695-21cut19:34:263
29925070,0irq/32-eth0-rx-11597-21kthreadcore21:24:303
29925070,0irq/32-eth0-rx-0-21swapper/321:13:463
74189960,0cyclictest0-21swapper/222:31:502
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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