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2024-04-15 - 19:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Mon Apr 15, 2024 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1367423930,0sleep30-21swapper/306:50:483
1383623726,0sleep00-21swapper/006:52:410
1383223625,0sleep10-21swapper/106:52:381
1382823526,0sleep20-21swapper/206:52:352
35160,0ktimersoftd/30-21swapper/311:58:453
35160,0ktimersoftd/30-21swapper/307:50:543
339960,0migration/39405-21kthreadcore09:20:323
339960,0migration/38186-21sh09:57:423
339960,0migration/35330-21sh09:36:533
339960,0migration/331810-21sh09:52:443
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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