You are here: Home / Projects / QA Farm Realtime / Latency plots / 
2022-01-23 - 09:14

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.4.229-rt200 (Profile)

Latency plot of system in rack #1, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Sun Jan 23, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312550600,0irq/31-eth10-21swapper/119:02:031
1176023627,0sleep30-21swapper/319:03:533
1194523526,0sleep20-21swapper/219:06:042
961622925,0sleep00-21swapper/019:01:460
12059991919,0cyclictest2654-21nvme21:04:423
12059991313,0cyclictest2654-21nvme21:59:063
12059991212,0cyclictest2654-21nvme23:37:083
12059991212,0cyclictest2654-21nvme22:47:283
12059991212,0cyclictest2654-21nvme22:10:333
12059991212,0cyclictest2654-21nvme21:45:383
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

Valid XHTML 1.0 Transitional