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2025-12-09 - 14:08
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot2.osadl.org (updated Tue Dec 09, 2025 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
264427776,0sleep00-21swapper/006:17:220
240325756,0sleep20-21swapper/206:14:522
2851994949,0cyclictest14597-21md0_resync08:47:171
244224342,0sleep10-21swapper/106:15:151
2852994038,0cyclictest14596-21md1_resync08:47:162
274523627,0sleep30-21swapper/306:18:253
2851991212,0cyclictest23871-21snmpd11:16:321
339980,0migration/36851-21kthreadcore09:44:113
8315070,0irq/26-0000:00:0-21swapper/311:19:153
8315070,0irq/26-0000:00:0-21swapper/311:12:063
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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