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2021-10-24 - 01:20

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.4.229-rt200 (Profile)

Latency plot of system in rack #1, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Sun Oct 24, 2021 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
191530,0ktimersoftd/128863-21perf19:08:341
3135423927,0sleep20-21swapper/219:07:192
3110923625,0sleep00-21swapper/019:04:290
3121523228,0sleep30-21swapper/319:05:443
31543991313,0cyclictest26681-21kworker/2:122:57:382
31543991212,0cyclictest26681-21kworker/2:120:19:422
31543991010,0cyclictest26681-21kworker/2:123:57:462
31543991010,0cyclictest26681-21kworker/2:123:20:502
31543991010,0cyclictest26681-21kworker/2:100:11:062
315439999,0cyclictest2654-21nvme21:57:572
315439988,0cyclictest2654-21nvme00:27:442
315439977,0cyclictest26681-21kworker/2:122:50:342
315439977,0cyclictest26681-21kworker/2:122:22:562
339960,0migration/31999-21sh21:13:373
315449966,0cyclictest0-21swapper/323:37:273
315449966,0cyclictest0-21swapper/300:11:593
315449960,0cyclictest0-21swapper/322:29:403
315449960,0cyclictest0-21swapper/300:23:013
315439966,0cyclictest26681-21kworker/2:122:02:142
315439966,0cyclictest2654-21nvme00:00:152
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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