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2024-12-01 - 21:07
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Sun Dec 01, 2024 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
539227574,0sleep10-21swapper/106:40:171
514825440,0sleep00-21swapper/006:37:280
540424030,0sleep30-21swapper/306:40:273
518623627,0sleep20-21swapper/206:37:582
329970,0watchdog/3299250irq/32-eth0-rx-09:49:003
329970,0watchdog/30-21swapper/311:55:513
329970,0watchdog/30-21swapper/311:47:513
329970,0watchdog/30-21swapper/310:42:083
29925070,0irq/32-eth0-rx-0-21swapper/310:25:013
55529960,0cyclictest16980-21diskmemload09:47:331
55519966,0cyclictest0-21swapper/007:21:460
55519960,0cyclictest0-21swapper/011:48:410
4160,0ktimersoftd/00-21swapper/011:01:140
339960,0migration/315457-21sh10:31:513
339960,0migration/310737-21kthreadcore11:26:363
329960,0watchdog/328790-21perl11:56:313
329960,0watchdog/315516-21grep07:06:403
329960,0watchdog/31261-21awk07:41:403
329960,0watchdog/30-21swapper/312:09:353
329960,0watchdog/30-21swapper/311:44:353
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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