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2021-07-26 - 18:01

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.4.229-rt200 (Profile)

Latency plot of system in rack #1, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Mon Jul 26, 2021 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
291450580,0irq/31-eth10-21swapper/107:19:081
1011224636,0sleep30-21swapper/307:22:173
982123727,0sleep20-21swapper/207:18:522
979723117,0sleep00-21swapper/007:18:340
28425060,0irq/33-eth0-tx-23428-21munin-node08:53:250
27160,0ktimersoftd/23026-21ssh09:56:462
149960,0migration/027462-21sh08:58:210
149960,0migration/01866-21needreboot08:08:140
102509960,0cyclictest0-21swapper/312:01:163
102509960,0cyclictest0-21swapper/311:02:373
102419960,0cyclictest0-21swapper/212:32:512
102379960,0cyclictest0-21swapper/112:20:541
102379960,0cyclictest0-21swapper/110:24:051
8305050,0irq/26-0000:00:6662-21sed12:17:522
8305050,0irq/26-0000:00:29487-21latency_hist12:07:522
8305050,0irq/26-0000:00:13622-21cat10:42:522
8305050,0irq/26-0000:00:0-21swapper/211:17:462
339950,0migration/330002-21sh09:49:173
339950,0migration/313993-21sh11:50:323
339950,0migration/31362-21unixbench-2d09:53:213
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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