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2024-05-27 - 17:26
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Mon May 27, 2024 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1768924025,0sleep00-21swapper/006:51:010
1779123728,0sleep30-21swapper/306:52:123
1192423625,0sleep20-21swapper/206:48:032
1760523423,0sleep10-21swapper/106:50:021
339960,0migration/35618-21sh08:57:503
339960,0migration/33763-21munin-node08:53:233
339960,0migration/330927-21sh09:29:563
339960,0migration/328722-21idleruntime10:48:063
339960,0migration/319668-21irqcore07:38:083
339960,0migration/314980-21sh12:21:403
339960,0migration/311887-21sh11:35:543
29935060,0irq/33-eth0-tx-25672-21munin-node07:43:010
29935060,0irq/33-eth0-tx-15027-21munin-node07:58:120
29925060,0irq/32-eth0-rx-2680-21perl10:13:023
29925060,0irq/32-eth0-rx-18884-21pmu-power11:38:103
29925060,0irq/32-eth0-rx-1124-21kthreadcore12:13:063
29925060,0irq/32-eth0-rx-10524-21ssh10:53:383
179089966,0cyclictest2546-21nvme07:57:081
179089966,0cyclictest2546-21nvme07:00:161
179089960,0cyclictest0-21swapper/111:41:111
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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