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2019-07-16 - 02:13

Intel(R) Core(TM)2 CPU 6600 @ 2.40GHz, Linux 4.4.39-rt50 (Profile)

Latency plot of system in rack #1, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack1slot2.osadl.org (updated Sat Jul 13, 2019 12:43:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
426991413,0cyclictest0-21swapper/010:27:330
426991413,0cyclictest0-21swapper/010:20:180
426991413,0cyclictest0-21swapper/009:41:410
426991413,0cyclictest0-21swapper/009:23:290
426991413,0cyclictest0-21swapper/008:28:240
426991413,0cyclictest0-21swapper/008:04:050
426991413,0cyclictest0-21swapper/007:39:450
426991413,0cyclictest0-21swapper/007:14:190
42699140,0cyclictest0-21swapper/011:40:450
42699140,0cyclictest0-21swapper/008:49:400
42699140,0cyclictest0-21swapper/008:40:430
191140,0ktimersoftd/131505-21munin-run09:25:371
191140,0ktimersoftd/10-21swapper/112:18:571
426991312,0cyclictest0-21swapper/012:31:430
426991312,0cyclictest0-21swapper/012:26:240
426991312,0cyclictest0-21swapper/012:21:420
426991312,0cyclictest0-21swapper/012:13:290
426991312,0cyclictest0-21swapper/011:47:250
426991312,0cyclictest0-21swapper/011:01:460
426991312,0cyclictest0-21swapper/011:00:050
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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