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2021-11-27 - 23:45

Intel(R) Xeon(R) CPU E3-1270 V2 @ 3.50GHz, Linux 4.4.229-rt200 (Profile)

Latency plot of system in rack #1, slot #2
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot2.osadl.org (updated Sat Nov 27, 2021 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312550690,0irq/31-eth10-21swapper/107:05:251
444823829,0sleep30-21swapper/307:04:213
456923725,0sleep20-21swapper/207:05:442
438423423,0sleep00-21swapper/007:03:380
4834991111,0cyclictest16653-21kworker/2:111:44:252
4834991010,0cyclictest2654-21nvme10:47:352
4834991010,0cyclictest16653-21kworker/2:111:20:072
48349999,0cyclictest16653-21kworker/2:112:21:032
48349999,0cyclictest16653-21kworker/2:107:28:232
48349988,0cyclictest2654-21nvme07:52:442
48349977,0cyclictest2654-21nvme08:20:062
48379960,0cyclictest0-21swapper/312:23:573
48349966,0cyclictest16653-21kworker/2:110:54:312
48349966,0cyclictest0-21swapper/209:49:242
48349960,0cyclictest0-21swapper/211:23:412
48349960,0cyclictest0-21swapper/210:16:132
48329966,0cyclictest2654-21nvme10:38:020
48329960,0cyclictest0-21swapper/012:08:480
30535060,0irq/33-eth0-tx-20871-21munin-node07:38:240
149960,0migration/08205-21sh09:45:540
149960,0migration/04314-21fschecks_time09:08:070
149960,0migration/022566-21diskmemload12:13:220
149960,0migration/02092-21idleruntime11:53:090
149960,0migration/019924-21munin-node11:38:080
8305050,0irq/26-0000:00:4054-21crond08:07:522
48379955,0cyclictest0-21swapper/312:03:183
48379950,0cyclictest0-21swapper/310:39:163
48349955,0cyclictest16653-21kworker/2:112:03:352
48349955,0cyclictest16653-21kworker/2:110:34:492
48349955,0cyclictest16653-21kworker/2:107:59:592
48349950,0cyclictest0-21swapper/211:28:532
48349950,0cyclictest0-21swapper/210:31:402
48349950,0cyclictest0-21swapper/210:02:202
48349950,0cyclictest0-21swapper/209:41:132
48349950,0cyclictest0-21swapper/209:36:192
48349950,0cyclictest0-21swapper/209:28:172
48339955,0cyclictest0-21swapper/112:06:041
48339955,0cyclictest0-21swapper/111:12:471
48339955,0cyclictest0-21swapper/111:07:341
48339954,0cyclictest3288-21ssh11:21:271
48339950,0cyclictest0-21swapper/110:34:191
48339950,0cyclictest0-21swapper/110:29:351
48339950,0cyclictest0-21swapper/109:52:031
48339950,0cyclictest0-21swapper/109:37:141
48339950,0cyclictest0-21swapper/109:21:091
48339950,0cyclictest0-21swapper/107:54:171
48329955,0cyclictest0-21swapper/010:25:230
48329955,0cyclictest0-21swapper/007:28:010
48329950,0cyclictest0-21swapper/011:50:500
48329950,0cyclictest0-21swapper/011:30:490
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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