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2026-05-19 - 02:51
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack1slot3.osadl.org (updated Tue May 19, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
71977999140,12cyclictest0-21swapper/323:50:133
71977999130,11cyclictest0-21swapper/323:55:093
71977999130,11cyclictest0-21swapper/320:15:113
719779991212,0cyclictest0-21swapper/300:15:133
719779991211,0cyclictest0-21swapper/321:15:153
719779991210,1cyclictest0-21swapper/321:05:123
71977999120,11cyclictest0-21swapper/322:10:133
71977999120,11cyclictest0-21swapper/321:20:113
719779991110,0cyclictest0-21swapper/321:50:103
719779991110,0cyclictest0-21swapper/321:50:013
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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