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2026-04-18 - 06:04
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack1slot3.osadl.org (updated Sat Apr 18, 2026 00:43:47)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4094986991310,2cyclictest0-21swapper/321:15:013
409498699128,1cyclictest0-21swapper/321:55:103
409498699120,1cyclictest0-21swapper/322:00:103
409498699120,1cyclictest0-21swapper/300:25:013
409498699120,11cyclictest0-21swapper/322:30:163
409498699119,1cyclictest0-21swapper/321:05:123
409498699119,1cyclictest0-21swapper/320:20:123
4094986991111,0cyclictest0-21swapper/321:35:183
409498699110,8cyclictest0-21swapper/323:55:173
409498699110,11cyclictest0-21swapper/320:05:163
409498699110,10cyclictest0-21swapper/322:35:123
409498699110,10cyclictest0-21swapper/320:45:173
409498699110,10cyclictest0-21swapper/320:00:173
409498699110,0cyclictest0-21swapper/323:20:103
409498699110,0cyclictest0-21swapper/322:40:113
409498699110,0cyclictest0-21swapper/319:55:113
409498699109,0cyclictest0-21swapper/319:30:113
4094986991010,0cyclictest0-21swapper/323:40:133
4094986991010,0cyclictest0-21swapper/323:30:173
4094986991010,0cyclictest0-21swapper/322:50:173
4094986991010,0cyclictest0-21swapper/319:30:013
4094986991010,0cyclictest0-21swapper/319:15:173
409498699100,9cyclictest0-21swapper/322:15:183
409498699100,0cyclictest4148038-21turbostat21:29:553
409498699100,0cyclictest0-21swapper/323:10:173
409498699100,0cyclictest0-21swapper/322:05:183
409498699100,0cyclictest0-21swapper/321:40:163
40949869999,0cyclictest0-21swapper/320:25:163
40949869999,0cyclictest0-21swapper/319:35:123
40949869999,0cyclictest0-21swapper/300:00:053
40949869998,0cyclictest0-21swapper/322:55:183
40949869998,0cyclictest0-21swapper/321:00:113
40949869990,9cyclictest0-21swapper/323:25:163
40949869990,8cyclictest0-21swapper/323:35:003
40949869990,8cyclictest0-21swapper/323:15:173
40949869990,8cyclictest0-21swapper/321:50:193
40949869988,0cyclictest0-21swapper/323:50:113
40949869988,0cyclictest0-21swapper/323:49:233
40949869988,0cyclictest0-21swapper/322:45:163
40949869988,0cyclictest0-21swapper/322:25:123
40949869988,0cyclictest0-21swapper/321:20:193
40949869988,0cyclictest0-21swapper/320:50:093
40949869988,0cyclictest0-21swapper/319:50:183
40949869988,0cyclictest0-21swapper/319:45:003
40949869980,0cyclictest0-21swapper/323:00:183
40949869980,0cyclictest0-21swapper/320:35:013
4093606281,4sleep30-21swapper/319:05:143
40949869977,0cyclictest0-21swapper/323:05:173
40949869977,0cyclictest0-21swapper/321:45:183
40949869977,0cyclictest0-21swapper/320:55:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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