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2024-04-19 - 23:41

OSADL QA Farm on Real-time of Mainline Linux

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Default latency plot of shadow in rack #1, slot #3

Rack #0/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #1/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #2/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #3/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #4/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #5/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #6/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #7/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #8/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #9/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #a/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #b/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #c/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #d/#0 #1 #2 #3 #4 #5 #6 #7 #8 -
Rack #e/#0 #1 #2 #3 #4 #5 #6 #7 #8 - Rack #f/#0 #1 #2 #3 #4 #5 #6 #7 #8 
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Click on a legend element to toggle display of that core, ctrl-click inverts display, shift-click enables all.

Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot3s.osadl.org (updated Tue May 26, 2020 00:45:01)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
14699916690,1668cyclictest1204-21snmpd19:33:437
14429916550,1654cyclictest1204-21snmpd23:49:350
14429916532,1650cyclictest1204-21snmpd21:44:090
14429916491,1647cyclictest1204-21snmpd21:34:070
14539916471,1645cyclictest29729-21sensors20:05:083
14539916470,1646cyclictest17480-21sensors19:40:093
14569916462,1643cyclictest1204-21snmpd00:09:374
14539916410,1640cyclictest10268-21sensors22:45:103
14539916400,1639cyclictest2939-21sensors19:10:093
14509916402,1637cyclictest1204-21snmpd23:54:362
14569916380,1637cyclictest30588-21sensors22:20:104
14459916361,1634cyclictest5417-21sensors22:35:091
14459916361,1634cyclictest5417-21sensors22:35:081
14539916320,1631cyclictest11198-21sensors21:40:113
14459916302,1627cyclictest1204-21snmpd23:09:261
14569916292,1626cyclictest1204-21snmpd22:49:234
14649916282,1625cyclictest1204-21snmpd21:19:056
14609916271,1625cyclictest1204-21snmpd19:48:465
14649916240,1623cyclictest1204-21snmpd21:04:026
14509916220,1621cyclictest23311-21sensors22:05:092
14459916201,1618cyclictest1204-21snmpd20:03:491
14539916190,1618cyclictest1204-21snmpd00:24:423
14509916151,1613cyclictest24737-21sensors19:55:082
14569916131,1611cyclictest13612-21sensors21:45:084
14509916131,1611cyclictest1204-21snmpd19:23:422
14509916120,1611cyclictest1204-21snmpd20:43:572
14429916122,1609cyclictest1204-21snmpd22:14:160
14539916112,1608cyclictest1204-21snmpd00:19:403
14459916101,1608cyclictest16684-21sensors20:45:081
14509916090,1608cyclictest19720-21sensors00:10:092
14509916082,1605cyclictest1204-21snmpd22:19:172
14459916070,1606cyclictest19900-21sensors19:45:081
14649916060,1605cyclictest12166-21sensors23:55:096
14649916041,1602cyclictest1204-21snmpd21:14:036
14699916030,1602cyclictest1204-21snmpd19:28:417
14609916031,1601cyclictest10206-21sensors19:25:095
14429915991,1597cyclictest1204-21snmpd23:14:270
14459915980,1597cyclictest1204-21snmpd20:54:001
14699915951,1593cyclictest28801-21sensors21:10:097
14539915871,1585cyclictest25729-21sensors22:10:073
14699915850,1584cyclictest22137-21sensors00:15:097
14509915850,1584cyclictest3795-21sensors21:25:082
14459915851,1583cyclictest1204-21snmpd23:29:311
14509915842,1581cyclictest32347-21sensors23:30:092
14569915832,1580cyclictest4922-21sensors23:40:094
14509915820,1581cyclictest1204-21snmpd22:54:242
14649915810,1580cyclictest27375-21sensors23:20:086
14649915802,1577cyclictest1204-21snmpd00:39:456
14459915781,1576cyclictest1204-21snmpd22:44:221
14509915761,1574cyclictest1204-21snmpd21:24:062
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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