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2022-06-27 - 17:05

x86 Intel Atom D2700 @2130 MHz, Linux 4.4.39-rt50 (Profile)

Latency plot of system in rack #1, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6.osadl.org (updated Mon Jun 27, 2022 12:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
91700,0rcu_sched29-21ksoftirqd/208:17:542
81700,0rcu_preempt3-21ksoftirqd/007:33:180
81690,0rcu_preempt29-21ksoftirqd/207:51:212
81690,0rcu_preempt29-21ksoftirqd/207:51:212
81640,0rcu_preempt29-21ksoftirqd/208:38:072
81630,0rcu_preempt20925-21latency_hist09:17:552
91620,0rcu_sched37-21ksoftirqd/307:37:543
81620,0rcu_preempt37-21ksoftirqd/308:13:093
81610,0rcu_preempt37-21ksoftirqd/307:13:073
81610,0rcu_preempt0-21swapper/211:43:192
81600,0rcu_preempt37-21ksoftirqd/311:28:253
81600,0rcu_preempt37-21ksoftirqd/310:42:543
81600,0rcu_preempt37-21ksoftirqd/308:07:263
81600,0rcu_preempt29-21ksoftirqd/211:58:072
3499600,0migration/330008-21runrttasks07:03:053
81590,0rcu_preempt37-21ksoftirqd/312:27:083
81590,0rcu_preempt37-21ksoftirqd/310:33:083
81590,0rcu_preempt37-21ksoftirqd/310:33:083
81590,0rcu_preempt37-21ksoftirqd/310:26:363
81590,0rcu_preempt37-21ksoftirqd/309:48:133
81590,0rcu_preempt29-21ksoftirqd/210:53:202
81580,0rcu_preempt29-21ksoftirqd/209:25:102
81580,0rcu_preempt29-21ksoftirqd/208:37:542
81570,0rcu_preempt37-21ksoftirqd/308:08:253
81570,0rcu_preempt29-21ksoftirqd/211:05:202
81570,0rcu_preempt29-21ksoftirqd/209:18:262
81570,0rcu_preempt29-21ksoftirqd/207:27:322
3187299573,0cyclictest0-21swapper/011:08:130
3187299573,0cyclictest0-21swapper/007:23:040
81560,0rcu_preempt37-21ksoftirqd/311:13:283
81560,0rcu_preempt37-21ksoftirqd/308:22:553
81560,0rcu_preempt37-21ksoftirqd/307:54:393
81560,0rcu_preempt3-21ksoftirqd/011:03:080
81560,0rcu_preempt29-21ksoftirqd/209:28:102
31882995623,0cyclictest37-21ksoftirqd/309:19:313
3187299563,0cyclictest19053-21tune2fs11:48:070
31872995623,0cyclictest29933-21nscd10:17:540
91550,0rcu_sched29-21ksoftirqd/207:17:542
81550,0rcu_preempt37-21ksoftirqd/311:48:183
81550,0rcu_preempt37-21ksoftirqd/311:07:543
81550,0rcu_preempt37-21ksoftirqd/310:53:133
81550,0rcu_preempt37-21ksoftirqd/310:07:403
81550,0rcu_preempt37-21ksoftirqd/308:23:253
81550,0rcu_preempt29-21ksoftirqd/212:34:072
81550,0rcu_preempt29-21ksoftirqd/212:29:242
81550,0rcu_preempt29-21ksoftirqd/212:29:242
81550,0rcu_preempt29-21ksoftirqd/212:23:572
81550,0rcu_preempt29-21ksoftirqd/211:33:222
81550,0rcu_preempt29-21ksoftirqd/211:33:222
81550,0rcu_preempt29-21ksoftirqd/207:20:532
3187299552,0cyclictest0-21swapper/009:08:270
3187299551,0cyclictest16643-21gltestperf07:48:080
3187299551,0cyclictest16643-21gltestperf07:48:080
81540,0rcu_preempt37-21ksoftirqd/312:21:253
81540,0rcu_preempt37-21ksoftirqd/312:03:333
81540,0rcu_preempt37-21ksoftirqd/311:33:193
81540,0rcu_preempt37-21ksoftirqd/311:33:193
81540,0rcu_preempt37-21ksoftirqd/309:14:063
81540,0rcu_preempt37-21ksoftirqd/309:10:143
81540,0rcu_preempt37-21ksoftirqd/308:38:253
81540,0rcu_preempt3-21ksoftirqd/010:12:550
81540,0rcu_preempt29-21ksoftirqd/212:09:302
81540,0rcu_preempt29-21ksoftirqd/211:53:092
81540,0rcu_preempt29-21ksoftirqd/211:25:392
81540,0rcu_preempt29-21ksoftirqd/210:41:002
81540,0rcu_preempt29-21ksoftirqd/208:47:562
81540,0rcu_preempt29-21ksoftirqd/208:28:222
81540,0rcu_preempt29-21ksoftirqd/207:39:552
81540,0rcu_preempt29-21ksoftirqd/207:08:462
3188299541,0cyclictest3906-21unixbench_multi08:33:253
3187299544,0cyclictest3757-21timerandwakeup08:33:230
3187299544,0cyclictest0-21swapper/009:28:130
3187299543,0cyclictest0-21swapper/010:07:460
31872995421,0cyclictest20376-21gltestperf10:33:100
31872995421,0cyclictest20376-21gltestperf10:33:100
3187299542,0cyclictest0-21swapper/008:48:140
81530,0rcu_preempt37-21ksoftirqd/311:58:073
81530,0rcu_preempt37-21ksoftirqd/310:43:103
81530,0rcu_preempt37-21ksoftirqd/309:58:073
81530,0rcu_preempt37-21ksoftirqd/309:06:153
81530,0rcu_preempt37-21ksoftirqd/308:53:533
81530,0rcu_preempt37-21ksoftirqd/308:48:123
81530,0rcu_preempt37-21ksoftirqd/308:43:213
81530,0rcu_preempt37-21ksoftirqd/308:43:213
81530,0rcu_preempt3-21ksoftirqd/010:18:080
81530,0rcu_preempt29-21ksoftirqd/209:12:542
81530,0rcu_preempt29-21ksoftirqd/208:03:192
81530,0rcu_preempt29-21ksoftirqd/207:03:192
3187299533,0cyclictest0-21swapper/011:38:230
3187299533,0cyclictest0-21swapper/010:56:350
3187299533,0cyclictest0-21swapper/009:23:240
3187299533,0cyclictest0-21swapper/008:53:270
3187299533,0cyclictest0-21swapper/007:18:250
31872995326,0cyclictest3-21ksoftirqd/012:37:150
31872995325,0cyclictest3-21ksoftirqd/011:13:390
31872995322,0cyclictest21671-21unixbench_multi07:58:260
3187299531,0cyclictest6902-21fschecks_count08:43:080
3187299531,0cyclictest6902-21fschecks_count08:43:080
91520,0rcu_sched21-21ksoftirqd/108:42:541
81520,0rcu_preempt37-21ksoftirqd/309:53:143
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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