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2024-06-20 - 07:49
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6 (updated Thu Jun 20, 2024 00:46:20)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5413
"cycles":100000000,5412
"load":"idle",5411
"condition":{5410
"clock":"2130"5408
"family":"x86",5407
"vendor":"Intel",5406
"processor":{5404
"dataset":"2024-01-08T15:39:30+0100"5402
"origin":"2024-01-08T12:43:23+0100",5401
"timestamps":{5400
"granularity":"microseconds"5398
8809:16:565396
84,09:16:525395
120,09:17:285394
117,09:17:255393
"maxima":[5392
009:15:285389
0,09:15:285388
0,09:15:285387
0,09:15:285386
0,09:15:285385
0,09:15:285384
0,09:15:285383
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0,09:15:285380
0,09:15:285379
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0,09:15:285364
0,09:15:285363
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0,09:15:285359
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0,09:15:285325
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0,09:15:285309
0,09:15:285308
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*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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