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2022-01-26 - 06:13

Intel(R) Atom(TM) CPU D2700 @ 2.13GHz, Linux 4.4.39-rt50 (Profile)

Latency plot of system in rack #1, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack1slot6.osadl.org (updated Wed Jan 26, 2022 00:43:31)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81670,0rcu_preempt21-21ksoftirqd/122:40:341
81660,0rcu_preempt37-21ksoftirqd/319:05:343
81600,0rcu_preempt29-21ksoftirqd/223:10:332
81570,0rcu_preempt37-21ksoftirqd/323:31:043
81570,0rcu_preempt3-21ksoftirqd/021:06:080
91560,0rcu_sched3-21ksoftirqd/023:00:330
91560,0rcu_sched29-21ksoftirqd/222:45:342
32332995619,0cyclictest11526-21timerwakeupswit22:06:080
91550,0rcu_sched29-21ksoftirqd/220:20:292
81550,0rcu_preempt37-21ksoftirqd/323:11:043
81550,0rcu_preempt37-21ksoftirqd/323:11:043
81550,0rcu_preempt29-21ksoftirqd/222:10:332
81540,0rcu_preempt37-21ksoftirqd/321:05:513
81540,0rcu_preempt29-21ksoftirqd/223:31:122
81540,0rcu_preempt29-21ksoftirqd/222:45:532
81540,0rcu_preempt29-21ksoftirqd/220:10:332
81540,0rcu_preempt29-21ksoftirqd/200:06:032
81540,0rcu_preempt21-21ksoftirqd/120:55:341
91530,0rcu_sched37-21ksoftirqd/320:15:343
91530,0rcu_sched3-21ksoftirqd/023:10:330
91530,0rcu_sched3-21ksoftirqd/021:00:340
91530,0rcu_sched29-21ksoftirqd/222:55:342
81530,0rcu_preempt37-21ksoftirqd/323:20:563
81530,0rcu_preempt37-21ksoftirqd/321:40:493
81530,0rcu_preempt37-21ksoftirqd/320:50:543
81530,0rcu_preempt3-21ksoftirqd/019:50:540
81530,0rcu_preempt29-21ksoftirqd/223:11:042
81530,0rcu_preempt29-21ksoftirqd/223:11:042
81530,0rcu_preempt29-21ksoftirqd/221:16:102
81530,0rcu_preempt29-21ksoftirqd/221:16:102
81530,0rcu_preempt29-21ksoftirqd/220:40:542
81530,0rcu_preempt29-21ksoftirqd/220:36:082
81530,0rcu_preempt29-21ksoftirqd/220:30:532
81530,0rcu_preempt29-21ksoftirqd/200:25:492
81530,0rcu_preempt21-21ksoftirqd/122:50:351
81530,0rcu_preempt21-21ksoftirqd/122:00:331
81530,0rcu_preempt21-21ksoftirqd/121:31:101
81530,0rcu_preempt21-21ksoftirqd/100:01:081
32332995319,0cyclictest2172-21unixbench_singl23:01:120
32332995314,0cyclictest3-21ksoftirqd/021:59:220
91520,0rcu_sched29-21ksoftirqd/222:00:292
91520,0rcu_sched21-21ksoftirqd/123:40:351
91520,0rcu_sched21-21ksoftirqd/123:05:331
91520,0rcu_sched21-21ksoftirqd/121:05:291
81520,0rcu_preempt37-21ksoftirqd/323:45:513
81520,0rcu_preempt37-21ksoftirqd/321:31:103
81520,0rcu_preempt37-21ksoftirqd/320:40:553
81520,0rcu_preempt37-21ksoftirqd/319:36:033
81520,0rcu_preempt29-21ksoftirqd/223:45:512
81520,0rcu_preempt29-21ksoftirqd/223:16:062
81520,0rcu_preempt29-21ksoftirqd/219:31:012
81520,0rcu_preempt29-21ksoftirqd/219:20:562
81520,0rcu_preempt29-21ksoftirqd/219:20:562
81520,0rcu_preempt21-21ksoftirqd/122:10:341
81520,0rcu_preempt21-21ksoftirqd/121:15:541
81520,0rcu_preempt21-21ksoftirqd/121:15:541
81520,0rcu_preempt21-21ksoftirqd/119:45:501
81520,0rcu_preempt21-21ksoftirqd/119:36:021
91510,0rcu_sched37-21ksoftirqd/323:10:333
91510,0rcu_sched30949-21crond20:20:341
91510,0rcu_sched29-21ksoftirqd/219:30:342
91510,0rcu_sched21-21ksoftirqd/123:15:341
81510,0rcu_preempt37-21ksoftirqd/323:56:003
81510,0rcu_preempt37-21ksoftirqd/323:45:293
81510,0rcu_preempt37-21ksoftirqd/322:40:533
81510,0rcu_preempt37-21ksoftirqd/321:21:023
81510,0rcu_preempt37-21ksoftirqd/320:46:013
81510,0rcu_preempt37-21ksoftirqd/320:36:053
81510,0rcu_preempt37-21ksoftirqd/320:25:293
81510,0rcu_preempt3-21ksoftirqd/020:05:510
81510,0rcu_preempt3-21ksoftirqd/019:40:540
81510,0rcu_preempt29-21ksoftirqd/222:31:002
81510,0rcu_preempt21-21ksoftirqd/123:20:561
81510,0rcu_preempt21-21ksoftirqd/120:45:591
81510,0rcu_preempt21-21ksoftirqd/120:30:561
81510,0rcu_preempt21-21ksoftirqd/120:10:551
32332995117,0cyclictest27136-21unixbench_singl00:01:120
81500,0rcu_preempt37-21ksoftirqd/323:25:553
81500,0rcu_preempt37-21ksoftirqd/322:15:503
81500,0rcu_preempt37-21ksoftirqd/322:15:503
81500,0rcu_preempt37-21ksoftirqd/321:26:093
81500,0rcu_preempt37-21ksoftirqd/320:06:013
81500,0rcu_preempt37-21ksoftirqd/300:26:093
81500,0rcu_preempt37-21ksoftirqd/300:00:543
81500,0rcu_preempt3-21ksoftirqd/022:45:340
81500,0rcu_preempt3-21ksoftirqd/022:20:340
81500,0rcu_preempt3-21ksoftirqd/022:20:340
81500,0rcu_preempt3-21ksoftirqd/021:20:530
81500,0rcu_preempt3-21ksoftirqd/019:10:550
81500,0rcu_preempt3-21ksoftirqd/019:05:340
81500,0rcu_preempt29-21ksoftirqd/223:36:022
81500,0rcu_preempt29-21ksoftirqd/222:25:482
81500,0rcu_preempt29-21ksoftirqd/222:20:342
81500,0rcu_preempt29-21ksoftirqd/222:20:342
81500,0rcu_preempt29-21ksoftirqd/221:46:092
81500,0rcu_preempt29-21ksoftirqd/221:41:042
81500,0rcu_preempt29-21ksoftirqd/221:36:042
81500,0rcu_preempt29-21ksoftirqd/221:11:092
81500,0rcu_preempt29-21ksoftirqd/221:01:102
81500,0rcu_preempt29-21ksoftirqd/219:55:552
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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