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2024-05-29 - 06:45
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6 (updated Wed May 29, 2024 00:46:22)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
"interval":200,5413
"cycles":100000000,5412
"load":"idle",5411
"condition":{5410
"clock":"2130"5408
"family":"x86",5407
"vendor":"Intel",5406
"processor":{5404
"dataset":"2024-01-08T15:39:30+0100"5402
"origin":"2024-01-08T12:43:23+0100",5401
"timestamps":{5400
"granularity":"microseconds"5398
8809:16:565396
84,09:16:525395
120,09:17:285394
117,09:17:255393
"maxima":[5392
009:15:285389
0,09:15:285388
0,09:15:285387
0,09:15:285386
0,09:15:285385
0,09:15:285384
0,09:15:285383
0,09:15:285382
0,09:15:285381
0,09:15:285380
0,09:15:285379
0,09:15:285378
0,09:15:285377
0,09:15:285376
0,09:15:285375
0,09:15:285374
0,09:15:285373
0,09:15:285372
0,09:15:285371
0,09:15:285370
0,09:15:285369
0,09:15:285368
0,09:15:285367
0,09:15:285366
0,09:15:285365
0,09:15:285364
0,09:15:285363
0,09:15:285362
0,09:15:285361
0,09:15:285360
0,09:15:285359
0,09:15:285358
0,09:15:285357
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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