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2021-01-24 - 12:38

Intel(R) Atom(TM) CPU D2700 @ 2.13GHz, Linux 4.4.39-rt50 (Profile)

Latency plot of system in rack #1, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot6.osadl.org (updated Sun Jan 24, 2021 00:43:32)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
81690,0rcu_preempt3-21ksoftirqd/019:33:180
81610,0rcu_preempt3-21ksoftirqd/022:03:230
81610,0rcu_preempt21-21ksoftirqd/100:38:091
91590,0rcu_sched29-21ksoftirqd/220:13:112
91580,0rcu_sched29-21ksoftirqd/219:53:112
81580,0rcu_preempt29-21ksoftirqd/221:18:092
81570,0rcu_preempt3-21ksoftirqd/022:33:250
81570,0rcu_preempt29-21ksoftirqd/219:18:152
81570,0rcu_preempt21-21ksoftirqd/122:03:301
3499570,0migration/319951-21timerwakeupswit19:03:293
81550,0rcu_preempt3-21ksoftirqd/022:38:180
1899550,0migration/120183-21runrttasks19:04:271
91540,0rcu_sched37-21ksoftirqd/320:53:113
81540,0rcu_preempt3-21ksoftirqd/022:48:100
81540,0rcu_preempt29-21ksoftirqd/223:33:252
81540,0rcu_preempt29-21ksoftirqd/222:53:112
81540,0rcu_preempt29-21ksoftirqd/219:38:192
81540,0rcu_preempt29-21ksoftirqd/219:38:192
81540,0rcu_preempt29-21ksoftirqd/200:33:272
20694995412,0cyclictest5773-21cat19:48:200
91530,0rcu_sched29-21ksoftirqd/223:08:102
81530,0rcu_preempt37-21ksoftirqd/320:38:333
81530,0rcu_preempt37-21ksoftirqd/319:58:103
81530,0rcu_preempt29-21ksoftirqd/222:48:092
81530,0rcu_preempt29-21ksoftirqd/222:32:352
81530,0rcu_preempt29-21ksoftirqd/222:32:352
81530,0rcu_preempt29-21ksoftirqd/222:18:232
81530,0rcu_preempt29-21ksoftirqd/220:50:502
81530,0rcu_preempt29-21ksoftirqd/219:48:172
2069499533,0cyclictest0-21swapper/023:18:100
20694995319,0cyclictest21255-21cstates23:13:120
20694995319,0cyclictest20019-21gltestperf21:48:220
20694995317,0cyclictest17952-21gltestperf21:43:160
2069499531,0cyclictest30162-21chrt22:13:140
81520,0rcu_preempt37-21ksoftirqd/322:53:103
81520,0rcu_preempt37-21ksoftirqd/320:28:183
81520,0rcu_preempt3-21ksoftirqd/019:03:180
81520,0rcu_preempt29-21ksoftirqd/223:51:102
81520,0rcu_preempt29-21ksoftirqd/221:28:262
81520,0rcu_preempt21-21ksoftirqd/121:53:331
81520,0rcu_preempt21-21ksoftirqd/121:18:281
2069499521,0cyclictest12618-21tune2fs00:13:150
81510,0rcu_preempt37-21ksoftirqd/323:03:173
81510,0rcu_preempt37-21ksoftirqd/322:28:263
81510,0rcu_preempt37-21ksoftirqd/322:28:263
81510,0rcu_preempt37-21ksoftirqd/319:43:293
81510,0rcu_preempt37-21ksoftirqd/319:33:173
81510,0rcu_preempt3-21ksoftirqd/022:58:100
81510,0rcu_preempt3-21ksoftirqd/019:58:310
81510,0rcu_preempt3-21ksoftirqd/000:08:100
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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