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2026-01-20 - 15:55
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 10 highest latencies:
System rack1slot8.osadl.org (updated Tue Jan 20, 2026 12:43:58)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
179032614592,15sleep00-21swapper/007:09:580
1794299536448,74cyclictest0-21swapper/007:10:150
1794399533438,82cyclictest18325-21awk07:10:151
228699950,12rtkit-daemon2285-21rtkit-daemon08:28:590
1794299915,14cyclictest0-21swapper/011:38:580
1794299877,27cyclictest0-21swapper/010:30:160
17942998719,16cyclictest0-21swapper/009:34:040
312542860,3sleep031259-21tail11:10:150
1794299848,27cyclictest0-21swapper/012:12:510
1794299845,29cyclictest0-21swapper/009:52:440
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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