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2026-02-09 - 15:35
[ 290.152] (II) VESA: driver for VESA chipsets: vesa
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 20 highest latencies:
System rack1slot8.osadl.org (updated Mon Feb 09, 2026 12:43:56)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
222969918761798,40cyclictest31974-21iostat07:35:190
219302610587,16sleep00-21swapper/007:06:450
22297995456,481cyclictest0-21swapper/107:35:191
22296995374,13cyclictest0-21swapper/007:10:050
2229799407321,80cyclictest0-21swapper/107:10:041
222969913013,110cyclictest0-21swapper/010:00:000
21063211530,27sleep10-21swapper/107:05:171
222969910188,8cyclictest0-21swapper/012:15:590
228699990,4rtkit-daemon2285-21rtkit-daemon12:15:131
22296999410,66cyclictest14627-21crond10:35:000
22296999018,51cyclictest0-21swapper/009:09:000
228699870,9rtkit-daemon0-21swapper/112:31:091
228699870,9rtkit-daemon0-21swapper/109:54:011
2229699875,29cyclictest0-21swapper/012:37:380
22296998722,42cyclictest0-21swapper/010:24:590
167022870,3sleep1251rcuc/112:35:161
228699860,9rtkit-daemon0-21swapper/109:24:241
228699860,13rtkit-daemon0-21swapper/111:49:081
228699860,12rtkit-daemon0-21swapper/108:34:391
2229699865,25cyclictest0-21swapper/011:49:020
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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