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2022-06-27 - 16:27

x86 Intel Atom Z530 @1600 MHz, Linux 3.12.61-rt81 (Profile)

Latency plot of system in rack #1, slot #8
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Compare latency of primary with shadow system
Characteristics of the 50 highest latencies:
System rack1slot8.osadl.org (updated Mon Jun 27, 2022 12:43:57)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
170612978958,13sleep10-21swapper/107:08:511
1721499755680,39cyclictest17194-21munin-run07:10:000
17214995402,526cyclictest22144-21ps07:24:520
1721599473407,27cyclictest0-21swapper/107:24:521
211999960,10rtkit-daemon0-21swapper/010:49:580
211999940,10rtkit-daemon0-21swapper/008:19:240
211999810,4rtkit-daemon2118-21rtkit-daemon12:31:301
211999800,5rtkit-daemon2118-21rtkit-daemon10:32:471
211999780,4rtkit-daemon2118-21rtkit-daemon07:10:141
211999760,4rtkit-daemon2118-21rtkit-daemon08:20:251
156222710,4sleep115621-21ssh09:48:341
211999690,4rtkit-daemon2118-21rtkit-daemon08:53:141
240002670,3sleep11721599cyclictest09:05:251
1721499645,53cyclictest0-21swapper/009:27:210
17214996334,24cyclictest0-21swapper/012:23:370
17214996331,27cyclictest0-21swapper/012:05:090
17214996241,17cyclictest0-21swapper/009:07:300
17214996133,20cyclictest0-21swapper/011:04:010
211999600,4rtkit-daemon2118-21rtkit-daemon11:49:180
1721499606,49cyclictest0-21swapper/012:14:230
1721499606,48cyclictest0-21swapper/011:15:010
1721499605,49cyclictest0-21swapper/009:45:280
17214996022,31cyclictest0-21swapper/009:20:260
17214996019,24cyclictest0-21swapper/012:00:540
211999590,4rtkit-daemon2118-21rtkit-daemon10:04:010
17214995937,18cyclictest0-21swapper/011:40:260
17214995936,16cyclictest0-21swapper/010:25:260
17214995924,29cyclictest0-21swapper/011:35:240
17214995921,32cyclictest0-21swapper/010:34:590
17214995916,38cyclictest0-21swapper/009:35:250
17214995913,39cyclictest0-21swapper/011:25:260
211999580,4rtkit-daemon2118-21rtkit-daemon11:56:480
1721599587,44cyclictest0-21swapper/111:28:341
1721499586,43cyclictest0-21swapper/011:21:330
1721499585,48cyclictest0-21swapper/011:15:150
17214995836,16cyclictest0-21swapper/010:45:000
17214995833,20cyclictest0-21swapper/011:34:240
17214995816,36cyclictest0-21swapper/010:18:550
17214995813,38cyclictest0-21swapper/012:39:510
17214995810,41cyclictest0-21swapper/008:51:210
85472574,13sleep10-21swapper/112:18:481
211999570,4rtkit-daemon2118-21rtkit-daemon11:06:080
1721599575,46cyclictest0-21swapper/109:51:511
1721599574,47cyclictest0-21swapper/112:38:311
1721499576,45cyclictest0-21swapper/010:35:080
1721499575,46cyclictest0-21swapper/008:09:380
17214995734,17cyclictest0-21swapper/009:40:180
17214995731,16cyclictest0-21swapper/010:13:130
1721499568,41cyclictest0-21swapper/009:50:210
1721499566,44cyclictest0-21swapper/009:34:560
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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