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2026-05-11 - 00:52
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sun May 10, 2026 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
299742920,0sleep10-21swapper/111:49:301
77702720,0sleep10-21swapper/109:17:101
251102610,0sleep00-21swapper/012:19:490
52142580,0sleep00-21swapper/010:37:050
34562580,0sleep1710-21NetworkManager11:10:581
247312580,0sleep30-21swapper/311:46:123
162812570,0sleep10-21swapper/108:00:141
36322550,0sleep10-21swapper/112:12:221
102852550,0sleep10-21swapper/111:53:241
63072540,1sleep26306-21awk07:35:162
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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