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2024-04-27 - 01:44
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Fri Apr 26, 2024 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
167402920,0sleep116704-21sshd11:06:441
43642790,0sleep0101ktimersoftd/009:18:010
148022770,2sleep22112199cyclictest08:10:162
124912760,0sleep10-21swapper/109:14:581
236522720,0sleep10-21swapper/109:28:151
35002630,0sleep00-21swapper/012:01:580
189602590,1sleep118947-21sshd09:19:501
287502540,1sleep30-21swapper/309:24:573
24472530,0sleep10-21swapper/112:12:331
159722530,1sleep115970-21sshd12:24:461
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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