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2024-12-10 - 11:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Tue Dec 10, 2024 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
141912940,0sleep014190-21sshd21:23:280
52842830,0sleep00-21swapper/022:52:160
210502740,0sleep20-21swapper/223:25:552
77362730,0sleep20-21swapper/200:15:332
291492650,0sleep10-21swapper/100:08:111
300042570,0sleep20-21swapper/221:44:052
267252550,0sleep20-21swapper/221:21:312
277872540,0sleep10-21swapper/100:31:301
277872540,0sleep10-21swapper/100:31:291
177302530,0sleep10-21swapper/121:39:441
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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