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2024-09-07 - 15:25
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Sat Sep 07, 2024 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
211312950,0sleep121130-21sshd09:14:201
75272910,0sleep27411-21sshd12:15:342
18482840,0sleep01847-21sshd11:42:590
202132540,1sleep220210-21sshd09:53:112
63992530,1sleep10-21swapper/109:05:121
63992530,1sleep10-21swapper/109:05:111
290292520,1sleep10-21swapper/109:18:221
13582520,0sleep20-21swapper/210:44:572
51612510,1sleep09-21ksoftirqd/012:32:570
18492510,0sleep20-21swapper/210:58:082
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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