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2023-12-11 - 02:54
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Mon Dec 11, 2023 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
312192920,0sleep20-21swapper/223:27:002
253542600,0sleep20-21swapper/222:47:302
255552580,0sleep10-21swapper/100:32:031
225992580,0sleep00-21swapper/022:08:360
225992580,0sleep00-21swapper/022:08:360
40782550,0sleep10-21swapper/121:16:021
319922540,0sleep10-21swapper/122:15:341
206002540,1sleep120727-21packagekitd21:46:141
166192520,0sleep00-21swapper/021:23:460
26832500,0sleep32681-21lspci23:27:413
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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