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2024-04-18 - 18:19
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 10 highest latencies:
System rack2slot0.osadl.org (updated Thu Apr 18, 2024 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1762121110,0sleep217587-21sshd12:31:472
298421040,0sleep10-21swapper/111:47:531
172372950,2sleep31847299cyclictest10:01:533
252732810,0sleep025272-21grep11:03:060
214542600,0sleep30-21swapper/309:39:383
23652560,1sleep12362-21sshd10:48:261
23652560,1sleep12362-21sshd10:48:251
135582560,0sleep20-21swapper/210:33:482
21342550,0sleep10-21swapper/111:20:101
62472540,0sleep10-21swapper/109:57:381
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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