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2022-10-04 - 02:22

x86 Intel Xeon E3-1220 @3100 MHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Tue Oct 04, 2022 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
230042600,0sleep00-21swapper/022:22:110
108582550,0sleep30-21swapper/320:35:223
105072530,0sleep30-21swapper/322:59:523
7412500,0sleep20-21swapper/223:21:382
36952490,0sleep20-21swapper/200:11:082
133122490,0sleep00-21swapper/022:44:140
164482470,0sleep10-21swapper/121:56:131
135662460,1sleep013569-21bash23:25:040
666224220,7sleep20-21swapper/219:09:532
660223919,6sleep10-21swapper/119:09:081
661123210,7sleep00-21swapper/019:09:150
65452308,7sleep30-21swapper/319:08:263
284882200,1sleep3643-21gdbus23:45:063
73182180,0sleep3391rcuc/321:30:003
681199180,1cyclictest1-21systemd21:23:033
64512180,0sleep10-21swapper/120:25:201
680799150,14cyclictest0-21swapper/222:21:282
6807991312,0cyclictest22232-21lspci21:25:252
679999130,12cyclictest614-21dbus-daemon23:35:471
64432130,0sleep10-21swapper/121:45:361
61322130,1sleep2321ktimersoftd/200:03:512
254982130,0sleep20-21swapper/223:11:322
252392130,0sleep10-21swapper/100:24:561
196722130,0sleep20-21swapper/222:45:332
106602130,0sleep20-21swapper/221:14:452
681199120,1cyclictest9776-21bash00:20:443
6807991211,0cyclictest2136-21lspci22:09:022
680799120,1cyclictest0-21swapper/221:30:182
680799120,11cyclictest23586-21sshd00:24:282
680799120,11cyclictest0-21swapper/200:32:282
679099120,1cyclictest19864-21sshd00:23:280
57062120,0sleep20-21swapper/223:47:212
681199110,1cyclictest20198-21bash21:16:533
681199110,10cyclictest0-21swapper/323:39:133
681199110,10cyclictest0-21swapper/321:41:233
681199110,0cyclictest0-21swapper/323:11:333
6807991110,0cyclictest18194-21lspci23:42:202
6807991110,0cyclictest16384-21lspci23:58:142
6807991110,0cyclictest0-21swapper/219:20:282
680799110,1cyclictest13382-21sshd23:08:382
680799110,10cyclictest0-21swapper/222:28:192
680799110,0cyclictest4244-21latency20:20:182
679999110,10cyclictest4195-21sshd23:46:561
679999110,10cyclictest0-21swapper/123:50:361
6790991110,0cyclictest0-21swapper/000:19:390
679099110,1cyclictest8812-21sshd22:50:580
679099110,1cyclictest27358-21sshd22:47:380
679099110,10cyclictest0-21swapper/022:17:490
679099110,10cyclictest0-21swapper/021:11:280
679099110,10cyclictest0-21swapper/000:39:180
681199109,0cyclictest0-21swapper/323:31:433
681199109,0cyclictest0-21swapper/323:01:233
681199109,0cyclictest0-21swapper/322:34:143
681199109,0cyclictest0-21swapper/322:34:133
681199109,0cyclictest0-21swapper/321:50:333
681199109,0cyclictest0-21swapper/321:38:243
681199109,0cyclictest0-21swapper/319:40:333
681199109,0cyclictest0-21swapper/300:36:443
681199108,1cyclictest17728-21memory23:50:233
681199100,0cyclictest0-21swapper/323:28:133
681199100,0cyclictest0-21swapper/322:44:233
681199100,0cyclictest0-21swapper/322:27:233
681199100,0cyclictest0-21swapper/319:45:343
680799109,0cyclictest19868-21lspci22:13:252
680799109,0cyclictest0-21swapper/222:15:282
680799109,0cyclictest0-21swapper/200:36:292
680799100,0cyclictest0-21swapper/223:50:182
680799100,0cyclictest0-21swapper/223:25:182
680799100,0cyclictest0-21swapper/221:21:082
679999109,0cyclictest0-21swapper/122:58:261
679999109,0cyclictest0-21swapper/121:05:261
679999108,1cyclictest1-21systemd00:13:071
679999108,1cyclictest0-21swapper/100:36:571
679999100,9cyclictest0-21swapper/123:21:561
679999100,9cyclictest0-21swapper/123:08:361
679999100,0cyclictest0-21swapper/121:51:071
679999100,0cyclictest0-21swapper/121:35:561
679999100,0cyclictest0-21swapper/121:11:161
679099109,0cyclictest0-21swapper/023:01:090
679099109,0cyclictest0-21swapper/021:50:580
679099100,9cyclictest0-21swapper/022:05:580
679099100,9cyclictest0-21swapper/021:17:390
679099100,0cyclictest0-21swapper/023:53:090
679099100,0cyclictest0-21swapper/022:27:280
679099100,0cyclictest0-21swapper/022:02:580
679099100,0cyclictest0-21swapper/021:56:580
679099100,0cyclictest0-21swapper/021:26:480
679099100,0cyclictest0-21swapper/000:31:280
7508290,0sleep20-21swapper/221:45:532
68119998,0cyclictest0-21swapper/323:08:133
68119998,0cyclictest0-21swapper/322:54:333
68119998,0cyclictest0-21swapper/320:05:033
68119997,1cyclictest576-17sedispatch22:02:443
68119990,0cyclictest0-21swapper/322:37:333
68079998,0cyclictest0-21swapper/223:15:282
68079998,0cyclictest0-21swapper/223:01:582
68079998,0cyclictest0-21swapper/221:00:192
68079998,0cyclictest0-21swapper/200:16:382
67999999,0cyclictest0-21swapper/123:11:571
67999998,0cyclictest0-21swapper/123:25:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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