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2021-08-04 - 20:54

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100 highest latencies:
System rack2slot0.osadl.org (updated Wed Aug 04, 2021 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186912740,0sleep30-21swapper/311:33:083
160902740,0sleep3401ktimersoftd/309:16:463
224732550,0sleep10-21swapper/111:25:531
269942530,0sleep30-21swapper/310:07:213
57872520,0sleep20-21swapper/209:22:152
42202520,0sleep00-21swapper/011:37:300
13142520,0sleep10-21swapper/110:09:081
60652500,0sleep30-21swapper/311:05:523
302422500,0sleep10-21swapper/110:32:021
170732480,0sleep20-21swapper/211:40:312
302532460,0sleep10-21swapper/109:28:231
257122817,7sleep20-21swapper/207:07:092
25272287,7sleep00-21swapper/007:06:350
72722513,7sleep10-21swapper/107:05:001
252522311,7sleep30-21swapper/307:06:343
25132160,0sleep30-21swapper/311:13:103
222412160,0sleep00-21swapper/012:05:490
192652150,0sleep20-21swapper/211:09:232
114372150,0sleep10-21swapper/111:55:201
315442130,0sleep10-21swapper/111:20:161
292299130,12cyclictest0-21swapper/112:12:121
2921991312,0cyclictest970-21snmpd10:39:150
2921991312,0cyclictest5978-21lspci10:42:000
292199130,1cyclictest1-21systemd12:37:100
292399120,11cyclictest614-21dbus-daemon10:52:192
292399120,11cyclictest10309-21bash10:43:092
292199120,1cyclictest0-21swapper/009:51:000
7592110,0sleep10-21swapper/112:16:351
2924991110,0cyclictest0-21swapper/312:38:523
292499110,10cyclictest0-21swapper/312:24:423
292499110,10cyclictest0-21swapper/312:24:413
292499110,10cyclictest0-21swapper/311:57:423
292499110,10cyclictest0-21swapper/309:56:413
292499110,0cyclictest0-21swapper/310:01:123
292399110,10cyclictest0-21swapper/212:11:402
292399110,10cyclictest0-21swapper/212:01:502
292399110,10cyclictest0-21swapper/211:36:402
292399110,10cyclictest0-21swapper/211:19:492
292399110,10cyclictest0-21swapper/210:29:102
292399110,10cyclictest0-21swapper/209:26:302
292299110,1cyclictest27512-21bash10:15:321
292299110,10cyclictest0-21swapper/112:20:331
292299110,10cyclictest0-21swapper/112:20:321
292299110,10cyclictest0-21swapper/111:39:131
292299110,10cyclictest0-21swapper/110:49:321
292299110,10cyclictest0-21swapper/109:54:121
292199110,10cyclictest0-21swapper/012:29:500
292199110,10cyclictest0-21swapper/011:53:000
292199110,10cyclictest0-21swapper/011:24:490
292199110,10cyclictest0-21swapper/011:09:590
292499109,0cyclictest0-21swapper/310:16:423
292499109,0cyclictest0-21swapper/310:14:523
292499109,0cyclictest0-21swapper/309:49:323
292499100,9cyclictest0-21swapper/312:16:223
292499100,9cyclictest0-21swapper/309:33:513
292499100,0cyclictest0-21swapper/310:57:023
292499100,0cyclictest0-21swapper/310:25:113
292399109,0cyclictest0-21swapper/212:35:402
292399100,9cyclictest0-21swapper/212:28:202
292399100,9cyclictest0-21swapper/210:57:402
292399100,9cyclictest0-21swapper/209:57:392
292399100,0cyclictest0-21swapper/212:20:302
292399100,0cyclictest0-21swapper/212:20:292
292399100,0cyclictest0-21swapper/211:51:002
292399100,0cyclictest0-21swapper/210:16:202
292399100,0cyclictest0-21swapper/210:10:502
292399100,0cyclictest0-21swapper/209:51:502
292399100,0cyclictest0-21swapper/209:40:002
292299109,0cyclictest0-21swapper/110:53:521
292299109,0cyclictest0-21swapper/110:22:021
292299109,0cyclictest0-21swapper/110:22:011
292299109,0cyclictest0-21swapper/110:10:011
292299109,0cyclictest0-21swapper/109:36:521
292299100,9cyclictest0-21swapper/109:12:021
292299100,0cyclictest0-21swapper/112:02:531
292299100,0cyclictest0-21swapper/111:51:331
292299100,0cyclictest0-21swapper/110:26:521
292199109,0cyclictest23402-21lspci10:46:140
292199109,0cyclictest0-21swapper/012:03:500
292199109,0cyclictest0-21swapper/010:21:300
292199109,0cyclictest0-21swapper/010:21:290
292199109,0cyclictest0-21swapper/009:21:290
292199108,1cyclictest17330-21lspci11:48:490
292199100,9cyclictest0-21swapper/011:40:400
292199100,0cyclictest0-21swapper/012:13:390
292199100,0cyclictest0-21swapper/010:26:200
29249998,0cyclictest0-21swapper/311:15:413
29249998,0cyclictest0-21swapper/310:43:013
29249998,0cyclictest0-21swapper/309:11:223
29249996,2cyclictest598-21avahi-daemon09:38:043
29239998,0cyclictest0-21swapper/210:47:302
29239998,0cyclictest0-21swapper/210:38:202
29239998,0cyclictest0-21swapper/210:24:202
29239998,0cyclictest0-21swapper/210:24:192
29239998,0cyclictest0-21swapper/210:08:592
29239998,0cyclictest0-21swapper/209:10:302
29229998,0cyclictest0-21swapper/112:34:421
29229998,0cyclictest0-21swapper/110:36:021
29229998,0cyclictest0-21swapper/109:44:221
29229998,0cyclictest0-21swapper/109:34:311
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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