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2022-06-30 - 22:32

x86 Intel Xeon E3-1220 @3100 MHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 100, Linux 4.9.20-rt16, x86_64 highest latencies:
System rack2slot0.osadl.org (updated Thu Jun 30, 2022 12:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
21452550,0sleep00-21swapper/011:40:140
258622540,2sleep02439599cyclictest09:14:040
69712530,0sleep30-21swapper/311:09:263
307272520,0sleep00-21swapper/012:27:320
24672510,1sleep2321ktimersoftd/210:12:092
209172490,0sleep10-21swapper/111:36:471
91812480,2sleep12440199cyclictest12:05:581
41712470,0sleep30-21swapper/312:37:003
2392424432,7sleep10-21swapper/107:05:371
318222410,0sleep00-21swapper/011:55:270
2398423018,7sleep20-21swapper/207:06:222
239502298,7sleep30-21swapper/307:05:543
2392322513,7sleep00-21swapper/007:05:360
27962190,0sleep00-21swapper/010:12:150
208082180,1sleep1241ktimersoftd/109:28:471
180132180,0sleep1231rcuc/109:51:571
319402170,2sleep32441899cyclictest09:55:203
205332170,0sleep20-21swapper/211:20:302
24418991513,1cyclictest598-21avahi-daemon11:49:053
269232140,0sleep30-21swapper/311:54:343
25402140,0sleep30-21swapper/310:44:183
127892140,0sleep30-21swapper/311:59:043
114282140,0sleep20-21swapper/209:42:212
24395991310,2cyclictest614-21dbus-daemon12:15:400
255552120,0sleep20-21swapper/209:53:582
2441899120,1cyclictest11482-21bash12:06:353
2441099120,1cyclictest0-21swapper/210:17:372
24401991210,1cyclictest27715-21lspci10:58:271
2440199120,1cyclictest8319-21sshd09:57:381
2440199120,11cyclictest10812-21sshd12:30:271
2441899110,10cyclictest0-21swapper/311:34:453
2441899110,10cyclictest0-21swapper/311:13:453
2441899110,10cyclictest0-21swapper/310:21:553
2441899110,10cyclictest0-21swapper/308:10:043
24410991110,0cyclictest0-21swapper/210:24:382
2441099110,10cyclictest0-21swapper/212:02:182
2441099110,10cyclictest0-21swapper/211:43:472
2441099110,10cyclictest0-21swapper/210:29:482
2441099110,10cyclictest0-21swapper/209:19:572
24401991110,0cyclictest9738-21lspci11:18:011
24401991110,0cyclictest33150irq/27-ahci[00010:31:331
24401991110,0cyclictest0-21swapper/112:26:581
2440199110,10cyclictest0-21swapper/111:59:281
2440199110,10cyclictest0-21swapper/111:27:381
2440199110,10cyclictest0-21swapper/111:20:381
2440199110,10cyclictest0-21swapper/111:01:281
2440199110,10cyclictest0-21swapper/110:10:181
2440199110,10cyclictest0-21swapper/110:07:071
2440199110,0cyclictest0-21swapper/109:22:581
2439599110,1cyclictest1067-21nfsd10:40:200
2439599110,10cyclictest0-21swapper/011:34:090
2439599110,10cyclictest0-21swapper/010:30:000
2441899109,0cyclictest0-21swapper/312:28:453
2441899109,0cyclictest0-21swapper/312:02:053
2441899109,0cyclictest0-21swapper/311:43:243
2441899109,0cyclictest0-21swapper/311:26:153
2441899108,1cyclictest14430-21sshd10:39:153
2441899100,9cyclictest0-21swapper/312:34:053
2441899100,9cyclictest0-21swapper/307:10:443
2441899100,0cyclictest0-21swapper/311:23:253
2441899100,0cyclictest0-21swapper/310:51:143
2441899100,0cyclictest0-21swapper/309:25:043
2441899100,0cyclictest0-21swapper/308:45:043
2441099109,0cyclictest0-21swapper/211:10:182
2441099109,0cyclictest0-21swapper/211:02:182
2441099109,0cyclictest0-21swapper/210:45:182
2441099109,0cyclictest0-21swapper/210:06:272
2441099108,1cyclictest0-21swapper/211:29:382
2441099100,0cyclictest0-21swapper/212:38:182
2441099100,0cyclictest0-21swapper/212:05:172
2440199109,0cyclictest15272-21lspci12:15:291
2440199109,0cyclictest0-21swapper/112:36:081
2440199109,0cyclictest0-21swapper/112:02:481
2440199109,0cyclictest0-21swapper/109:43:271
2440199109,0cyclictest0-21swapper/109:18:271
2440199109,0cyclictest0-21swapper/108:35:171
2440199100,0cyclictest0-21swapper/111:53:381
2440199100,0cyclictest0-21swapper/111:30:271
2440199100,0cyclictest0-21swapper/110:54:381
2440199100,0cyclictest0-21swapper/110:00:481
2439599109,0cyclictest0-21swapper/011:21:300
2439599109,0cyclictest0-21swapper/009:24:400
2439599108,1cyclictest31299-21sshd09:31:090
2439599100,9cyclictest0-21swapper/011:00:500
2439599100,9cyclictest0-21swapper/009:26:500
2439599100,9cyclictest0-21swapper/009:15:390
2439599100,0cyclictest0-21swapper/011:25:400
2439599100,0cyclictest0-21swapper/011:17:200
244189998,0cyclictest0-21swapper/312:16:043
244189998,0cyclictest0-21swapper/310:34:053
244189998,0cyclictest0-21swapper/310:25:243
244189998,0cyclictest0-21swapper/309:46:353
244189998,0cyclictest0-21swapper/309:31:353
244109998,0cyclictest0-21swapper/211:32:282
244109998,0cyclictest0-21swapper/210:33:182
244109998,0cyclictest0-21swapper/209:00:182
244109998,0cyclictest0-21swapper/209:00:172
244019998,0cyclictest0-21swapper/110:35:481
244019998,0cyclictest0-21swapper/109:37:581
244019998,0cyclictest0-21swapper/107:50:161
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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