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2025-07-04 - 02:10
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Fri Jul 04, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
246082750,2sleep03025799cyclictest23:23:260
177132690,0sleep00-21swapper/023:01:160
81092580,0sleep20-21swapper/222:07:502
282122560,0sleep30-21swapper/322:22:103
298212540,1sleep029818-21lspci22:22:180
226132540,0sleep10-21swapper/122:00:001
319662530,0sleep00-21swapper/023:11:480
281542520,1sleep2321ktimersoftd/222:37:392
259462520,0sleep341-21ksoftirqd/323:35:393
221252520,0sleep322121-21lspci21:16:483
296642510,0sleep2321ktimersoftd/222:34:452
226892510,0sleep00-21swapper/022:40:130
210392510,1sleep0616-17auditd00:39:200
152702510,0sleep00-21swapper/022:02:240
152702510,0sleep00-21swapper/022:02:230
81192500,0sleep30-21swapper/322:50:563
282852490,0sleep20-21swapper/200:10:062
265342490,1sleep341-21ksoftirqd/322:25:093
251772490,0sleep20-21swapper/223:08:062
87452480,0sleep10-21swapper/119:35:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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