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2024-05-30 - 01:59
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Wed May 29, 2024 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
175742980,1sleep217573-21sshd09:17:272
210512780,0sleep20-21swapper/210:28:092
135992580,0sleep10-21swapper/109:54:071
98152560,0sleep20-21swapper/210:43:302
294382560,0sleep30-21swapper/311:38:393
179592530,0sleep30-21swapper/309:41:193
325612520,0sleep10-21swapper/109:12:291
178882520,0sleep30-21swapper/309:54:333
91412510,3sleep233-21ksoftirqd/212:12:262
239952510,1sleep125-21ksoftirqd/109:48:381
217162510,0sleep10-21swapper/112:23:061
157632510,0sleep10-21swapper/109:27:031
132582510,0sleep2311rcuc/212:03:092
38172500,0sleep00-21swapper/010:10:040
289892500,0sleep10-21swapper/112:17:381
229812500,0sleep00-21swapper/009:58:220
67102490,0sleep10-21swapper/111:52:471
31432480,0sleep10-21swapper/109:43:091
98502470,0sleep20-21swapper/209:43:502
152032470,0sleep315201-21lspci11:33:543
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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