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2023-12-08 - 00:13
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu Dec 07, 2023 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
44152810,0sleep30-21swapper/310:06:013
301572550,0sleep00-21swapper/009:21:080
301622540,0sleep30-21swapper/309:37:383
279682540,0sleep30-21swapper/311:26:483
133702540,0sleep20-21swapper/210:18:382
107732510,0sleep00-21swapper/009:56:080
302102500,0sleep30-21swapper/311:16:113
296842500,1sleep30-21swapper/311:05:173
244192500,0sleep30-21swapper/311:59:163
85322490,0sleep341-21ksoftirqd/309:55:443
258602490,0sleep30-21swapper/310:20:353
317792480,1sleep231773-21sshd11:33:002
292602480,0sleep10-21swapper/112:10:561
253132480,0sleep00-21swapper/010:53:330
77952450,0sleep10-21swapper/112:01:491
260192440,2sleep1503499cyclictest10:42:401
267302370,0sleep20-21swapper/211:04:482
456723210,7sleep20-21swapper/207:07:222
453023210,7sleep00-21swapper/007:07:040
44412265,6sleep30-21swapper/307:06:223
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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