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2019-11-15 - 10:51

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Fri Nov 15, 2019 00:44:11)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
186892700,0sleep00-21swapper/000:25:020
181162680,0sleep20-21swapper/222:11:192
252722570,0sleep30-21swapper/300:03:543
287912550,0sleep00-21swapper/023:36:360
60952540,1sleep30-21swapper/321:36:003
113392540,0sleep20-21swapper/200:23:432
247782530,0sleep00-21swapper/000:20:170
222152520,2sleep122202-21sshd21:22:121
57552510,0sleep10-21swapper/122:59:241
55352510,0sleep00-21swapper/023:15:530
43782510,0sleep2311rcuc/223:21:162
2909425128,7sleep10-21swapper/119:05:351
23752510,0sleep10-21swapper/119:20:041
2942525029,7sleep00-21swapper/019:09:390
2941525038,7sleep20-21swapper/219:09:332
256942500,2sleep12970899cyclictest00:26:031
256652500,0sleep00-21swapper/021:28:240
136572500,0sleep30-21swapper/321:31:483
60212480,0sleep10-21swapper/122:42:421
46482480,0sleep10-21swapper/100:39:201
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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