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2021-06-17 - 19:08

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu Jun 17, 2021 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
78822540,1sleep3391rcuc/312:31:403
26272540,0sleep30-21swapper/311:34:203
147372540,0sleep20-21swapper/211:21:012
95312520,0sleep00-21swapper/011:03:530
236782520,0sleep323684-21nfsd411:15:193
131872520,0sleep013188-21nfsd410:00:170
180092510,0sleep00-21swapper/008:25:230
283842500,0sleep20-21swapper/212:28:552
109152500,0sleep20-21swapper/209:35:372
74572490,0sleep30-21swapper/308:00:363
137082490,0sleep10-21swapper/112:09:151
121852490,0sleep30-21swapper/311:04:373
122112450,0sleep30-21swapper/310:56:193
178372430,0sleep00-21swapper/009:45:200
1771524029,6sleep10-21swapper/107:07:291
1791023411,7sleep30-21swapper/307:09:513
1789923121,6sleep20-21swapper/207:09:422
177902297,7sleep00-21swapper/007:08:240
100142210,0sleep20-21swapper/212:32:152
80332190,2sleep11803599cyclictest09:11:001
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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