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2019-07-16 - 02:13

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Tue Jul 16, 2019 00:44:14)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
1438121080,0sleep30-21swapper/323:09:213
193812740,2sleep02993599cyclictest21:33:160
128102590,0sleep20-21swapper/200:24:242
48692530,0sleep30-21swapper/319:25:073
2962925230,7sleep00-21swapper/019:09:230
2956925231,7sleep20-21swapper/219:08:372
48372510,0sleep10-21swapper/121:30:001
105092500,0sleep10-21swapper/121:38:411
2938924726,7sleep10-21swapper/119:06:161
147422470,0sleep20-21swapper/223:24:292
246622460,0sleep10-21swapper/121:19:431
209892460,0sleep00-21swapper/023:18:190
209892460,0sleep00-21swapper/023:18:190
115822460,0sleep30-21swapper/322:45:543
2941624432,7sleep30-21swapper/319:06:383
203642440,2sleep22993799cyclictest22:18:102
29932380,0sleep30-21swapper/322:14:153
14332370,0sleep3391rcuc/300:14:083
111022250,0sleep00-21swapper/023:00:490
108732190,0sleep30-21swapper/322:53:273
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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