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2021-09-27 - 05:48

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Mon Sep 27, 2021 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
194412750,1sleep3401ktimersoftd/323:14:593
189722710,0sleep00-21swapper/021:21:220
37132530,0sleep00-21swapper/023:51:210
33702490,0sleep30-21swapper/322:46:203
1956724938,6sleep10-21swapper/119:07:141
146622480,0sleep10-21swapper/121:36:251
137212440,0sleep20-21swapper/223:13:262
1951923928,6sleep20-21swapper/219:06:392
1944222412,7sleep30-21swapper/319:05:443
1946822312,7sleep00-21swapper/019:06:010
257632210,0sleep20-21swapper/221:31:052
43292200,0sleep10-21swapper/123:35:281
192812170,0sleep00-21swapper/000:35:300
118062170,0sleep0111rcuc/022:56:340
102732170,0sleep10-21swapper/123:04:321
21692150,1sleep0101ktimersoftd/000:23:250
19902991514,0cyclictest19047-21lspci21:29:421
231222140,1sleep323124-21cpuspeed_turbos23:40:143
19905991413,0cyclictest14776-21lspci23:46:002
19905991413,0cyclictest11626-21lspci00:25:332
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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