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2024-04-20 - 08:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Sat Apr 20, 2024 00:43:50)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
2888521010,2sleep32285699cyclictest23:03:053
310432980,0sleep10-21swapper/100:30:541
72502970,2sleep22284999cyclictest23:30:202
107042940,2sleep32285699cyclictest23:16:033
87722910,0sleep10-21swapper/123:56:501
131582770,0sleep0111rcuc/021:30:460
11272560,0sleep00-21swapper/023:53:160
20412550,0sleep10-21swapper/121:38:311
263212540,0sleep226317-21sshd21:26:122
18742540,2sleep275650irq/25-eno1-tx-21:21:062
183832540,0sleep318381-21sshd21:28:253
83612530,0sleep20-21swapper/223:10:042
69682530,2sleep02283899cyclictest22:39:420
69132530,0sleep10-21swapper/121:05:241
48912530,0sleep10-21swapper/123:41:561
237172530,0sleep10-21swapper/121:55:311
2243325343,6sleep00-21swapper/019:06:130
152092530,1sleep215208-21bash00:03:352
12072530,1sleep31198-21lspci00:08:423
190502520,0sleep30-21swapper/321:34:173
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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