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2025-07-07 - 21:24
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Mon Jul 07, 2025 12:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
9502780,1sleep0700-21gdbus09:57:500
101802720,0sleep10-21swapper/109:48:261
207312600,0sleep20-21swapper/210:37:192
191042570,0sleep019099-21lspci12:12:560
250322560,1sleep225013-21bash09:56:562
84582550,0sleep10-21swapper/110:46:141
292372540,0sleep10-21swapper/109:57:231
234022540,0sleep30-21swapper/312:30:353
22152540,2sleep21292299cyclictest10:41:582
279452530,0sleep30-21swapper/310:45:003
32272520,1sleep13151-21sshd11:10:051
17962520,1sleep31798-21bash09:50:483
78372510,0sleep00-21swapper/010:46:090
287632510,1sleep21-21systemd09:19:512
169082510,1sleep016909-21sshd09:25:140
38522500,1sleep03855-21bash10:42:080
193052500,0sleep30-21swapper/310:47:283
172092500,0sleep10-21swapper/110:03:001
141742490,0sleep10-21swapper/109:31:521
12642490,0sleep10-21swapper/111:06:211
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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