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2024-09-12 - 23:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Thu Sep 12, 2024 12:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
34922830,2sleep0392199cyclictest11:03:240
180072710,0sleep10-21swapper/111:07:521
9302560,2sleep2393399cyclictest12:25:482
163692540,0sleep30-21swapper/310:27:013
136662540,0sleep30-21swapper/312:26:573
122192540,0sleep30-21swapper/312:03:543
305242530,0sleep30-21swapper/312:05:263
194812530,0sleep00-21swapper/009:49:090
327622520,0sleep00-21swapper/009:40:400
254572520,0sleep10-21swapper/109:23:551
214422520,0sleep021432-21lspci09:20:090
138032510,0sleep113798-21bash11:44:091
61042500,0sleep0111rcuc/012:11:520
192452500,0sleep10-21swapper/109:19:581
193052470,0sleep30-21swapper/311:47:283
48602460,2sleep3393899cyclictest10:32:063
213942450,0sleep20-21swapper/209:09:022
97942430,1sleep39793-21irqstats09:35:143
346324338,3sleep10-21swapper/107:05:331
83242380,0sleep20-21swapper/209:47:592
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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