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2024-07-27 - 07:53
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Sat Jul 27, 2024 00:43:48)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
324322750,1sleep232429-21sshd21:43:192
153912610,1sleep10-21swapper/122:57:281
317432600,0sleep30-21swapper/300:27:173
94702550,0sleep10-21swapper/100:07:301
179662550,0sleep00-21swapper/021:44:540
242962540,1sleep31643099cyclictest22:52:383
216472540,0sleep3401ktimersoftd/321:20:063
192012530,1sleep20-21swapper/221:36:352
151812530,0sleep00-21swapper/022:57:270
295372510,0sleep30-21swapper/322:19:263
6022500,0sleep00-21swapper/000:40:010
307792500,0sleep10-21swapper/123:49:271
290392500,0sleep30-21swapper/322:39:003
250822500,1sleep2311rcuc/221:28:462
204042500,0sleep30-21swapper/321:39:323
165502500,0sleep10-21swapper/100:28:561
151342500,0sleep2311rcuc/223:34:022
32942490,0sleep20-21swapper/223:24:372
212642490,0sleep20-21swapper/223:48:362
39642480,0sleep20-21swapper/200:33:502
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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