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2025-03-18 - 04:41
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Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 20 highest latencies:
System rack2slot0.osadl.org (updated Tue Mar 18, 2025 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
535421050,0sleep2500299cyclictest23:17:492
239572620,0sleep00-21swapper/021:10:060
96562610,0sleep20-21swapper/221:51:582
129112610,0sleep20-21swapper/222:13:412
287082590,0sleep30-21swapper/300:06:283
55292580,0sleep10-21swapper/121:33:101
278542580,0sleep10-21swapper/122:24:131
154282580,0sleep20-21swapper/200:20:292
219302540,1sleep1231rcuc/121:09:351
304062530,1sleep130408-21kworker/u8:121:35:261
280542520,0sleep10-21swapper/121:47:371
18452520,0sleep10-21swapper/123:57:451
178272520,0sleep10-21swapper/122:04:581
97302510,0sleep30-21swapper/300:26:353
39502510,0sleep10-21swapper/123:33:021
172322510,0sleep10-21swapper/100:27:211
70172500,0sleep20-21swapper/219:15:002
283552500,0sleep10-21swapper/121:20:051
262752500,0sleep30-21swapper/323:41:173
222182500,1sleep222216-21ntp_states23:10:122
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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