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2021-01-20 - 10:05

Intel(R) Xeon(R) CPU E31220 @ 3.10GHz, Linux 4.19.1-rt3 (Profile)

Latency plot of system in rack #2, slot #0
Data to construct the above plot have been generated using the RT test utility cyclictest.
Unexpectedly long latencies may be caused by SMIs
Command line: cyclictest -l100000000 -m -Sp99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes, lowest P state: performance
Characteristics of the 50 highest latencies:
System rack2slot0.osadl.org (updated Wed Jan 20, 2021 00:43:49)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
17942780,0sleep30-21swapper/323:40:103
246602620,0sleep20-21swapper/223:21:232
246602620,0sleep20-21swapper/223:21:232
122722570,0sleep20-21swapper/222:39:342
136952540,0sleep20-21swapper/223:30:482
150502530,0sleep10-21swapper/123:25:191
73372520,0sleep00-21swapper/000:09:440
259322520,0sleep00-21swapper/021:56:180
98072500,0sleep10-21swapper/123:47:171
157192500,0sleep30-21swapper/321:25:533
153502490,0sleep30-21swapper/321:54:383
250732470,0sleep20-21swapper/219:55:112
117922470,0sleep20-21swapper/219:15:112
315342450,1sleep031533-21smartctl22:20:050
186982420,2sleep2791199cyclictest21:49:312
68852329,7sleep30-21swapper/319:05:123
76042309,7sleep00-21swapper/019:07:250
758122716,7sleep20-21swapper/219:07:072
751022312,6sleep10-21swapper/119:06:181
174912190,0sleep30-21swapper/300:28:293
321962180,0sleep30-21swapper/321:11:513
65032170,0sleep20-21swapper/221:24:282
251382170,2sleep0790099cyclictest22:35:550
18532170,1sleep21852-21sshd00:14:262
104242160,0sleep10-21swapper/122:10:331
9182150,0sleep00-21swapper/022:03:230
164332150,0sleep10-21swapper/121:37:411
16682140,0sleep10-21swapper/123:57:141
108952130,0sleep10-21swapper/121:25:071
791199120,11cyclictest0-21swapper/200:04:472
790699120,1cyclictest25390-21sshd00:29:571
790099120,1cyclictest0-21swapper/020:05:120
56072120,1sleep05612-21latency23:35:110
791799119,1cyclictest7012-21bash23:06:543
791799119,1cyclictest0-21swapper/322:20:143
7917991110,0cyclictest0-21swapper/323:21:143
7917991110,0cyclictest0-21swapper/323:21:143
791799110,10cyclictest0-21swapper/323:03:143
791799110,10cyclictest0-21swapper/322:16:243
791199110,10cyclictest0-21swapper/223:51:272
791199110,10cyclictest0-21swapper/222:31:572
790699119,1cyclictest15955-21sshd22:57:081
790699110,1cyclictest2126-21sshd23:23:121
790699110,1cyclictest2126-21sshd23:23:121
790699110,1cyclictest0-21swapper/123:53:031
790699110,10cyclictest0-21swapper/123:02:371
790099119,1cyclictest19732-21sshd23:03:320
790099110,1cyclictest0-21swapper/023:53:020
790099110,10cyclictest0-21swapper/023:42:430
790099110,10cyclictest0-21swapper/023:28:320
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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