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2021-10-17 - 21:46

Intel(R) Celeron(R) M processor 1.50GHz, Linux 3.2.39-rt59 (Profile)

Latency plot of system in rack #2, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the highest latencies:
System rack2slot6.osadl.org (updated Sun Oct 17, 2021 12:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
4111995324cyclictest0-21swapper12:28:490
4111995231cyclictest0-21swapper15:07:180
4111995111cyclictest0-21swapper13:07:340
4111995030cyclictest0-21swapper12:58:520
4111995014cyclictest18262-21kworker/0:214:32:310
4111994923cyclictest18262-21kworker/0:215:20:210
4111994824cyclictest0-21swapper14:40:560
4111994814cyclictest18262-21kworker/0:214:33:150
4111994814cyclictest18262-21kworker/0:213:21:250
4111994813cyclictest18262-21kworker/0:214:50:230
4111994810cyclictest0-21swapper13:57:190
4111994810cyclictest0-21swapper13:13:150
4111994810cyclictest0-21swapper12:44:420
4111994720cyclictest0-21swapper14:46:200
4111994714cyclictest18262-21kworker/0:213:35:470
4111994714cyclictest18262-21kworker/0:212:22:470
4111994713cyclictest18262-21kworker/0:212:36:180
4111994711cyclictest0-21swapper12:41:250
4111994710cyclictest0-21swapper14:08:160
4111994710cyclictest0-21swapper14:07:570
411199469cyclictest0-21swapper12:16:390
4111994615cyclictest18262-21kworker/0:213:41:390
4111994612cyclictest32168-21grep15:33:240
4111994612cyclictest18262-21kworker/0:214:53:370
4111994610cyclictest0-21swapper15:13:480
4111994610cyclictest0-21swapper14:59:300
4111994610cyclictest0-21swapper14:14:130
411199459cyclictest0-21swapper15:11:430
411199459cyclictest0-21swapper14:00:160
411199459cyclictest0-21swapper13:46:340
411199459cyclictest0-21swapper13:28:590
411199459cyclictest0-21swapper13:10:420
411199458cyclictest0-21swapper12:54:050
4111994524cyclictest0-21swapper14:25:210
4111994514cyclictest18262-21kworker/0:215:38:130
4111994514cyclictest18262-21kworker/0:215:24:490
4111994514cyclictest18262-21kworker/0:214:20:100
4111994514cyclictest18262-21kworker/0:212:23:190
4111994511cyclictest0-21swapper13:23:160
4111994510cyclictest0-21swapper13:48:150
4111994415cyclictest18262-21kworker/0:215:30:020
4111994414cyclictest18262-21kworker/0:212:49:000
4111993710cyclictest12076-21munin-node12:03:360
4111993510cyclictest2929-21munin-node11:38:330
411199349cyclictest31ksoftirqd/010:15:100
4111993424cyclictest10244-21munin-node11:58:320
4111993410cyclictest26141-21munin-node11:13:440
411199339cyclictest31ksoftirqd/011:29:330
411199339cyclictest0-21swapper11:48:240
411199339cyclictest0-21swapper10:55:350
4111993312cyclictest0-21swapper11:27:010
4111993311cyclictest6031-21munin-node10:18:410
4111993311cyclictest0-21swapper10:42:360
4111993310cyclictest8421-21munin-node11:53:360
4111993310cyclictest31ksoftirqd/010:29:250
4111993310cyclictest24305-21munin-node11:08:430
4111993310cyclictest0-21swapper12:09:320
4111993310cyclictest0-21swapper11:35:480
4111993310cyclictest0-21swapper10:58:530
4111993310cyclictest0-21swapper10:51:570
4111993310cyclictest0-21swapper10:47:360
4111993310cyclictest0-21swapper10:23:590
411199329cyclictest11509-21munin-node10:33:390
411199329cyclictest0-21swapper11:18:340
4111993212cyclictest0-21swapper11:45:300
4111993210cyclictest0-21swapper11:03:290
4111992920cyclictest4109-21cyclictest10:13:260
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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