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2021-09-28 - 09:49

Intel(R) Celeron(R) M processor 1.50GHz, Linux 3.2.39-rt59 (Profile)

Latency plot of system in rack #2, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100 highest latencies:
System rack2slot6.osadl.org (updated Tue Sep 28, 2021 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
20340995928cyclictest0-21swapper03:14:340
20340995729cyclictest0-21swapper02:16:540
20340995725cyclictest0-21swapper01:08:390
20340995628cyclictest0-21swapper02:55:560
20340995627cyclictest18939-21memory02:19:580
20340995627cyclictest0-21swapper01:36:210
20340995626cyclictest0-21swapper00:45:380
20340995531cyclictest0-21swapper01:47:120
20340995529cyclictest0-21swapper01:51:520
20340995528cyclictest0-21swapper02:02:300
20340995527cyclictest0-21swapper03:40:480
20340995527cyclictest0-21swapper02:07:450
20340995527cyclictest0-21swapper01:02:400
20340995526cyclictest0-21swapper03:59:020
20340995526cyclictest0-21swapper03:26:550
20340995525cyclictest0-21swapper03:37:220
20340995525cyclictest0-21swapper03:29:430
20340995525cyclictest0-21swapper02:45:360
20340995523cyclictest0-21swapper03:10:010
20340995432cyclictest0-21swapper01:14:470
20340995431cyclictest0-21swapper03:05:230
20340995431cyclictest0-21swapper03:00:150
20340995430cyclictest4603-21irqstats00:50:030
20340995429cyclictest0-21swapper01:40:080
20340995427cyclictest0-21swapper02:50:200
20340995427cyclictest0-21swapper02:25:260
20340995426cyclictest0-21swapper04:09:070
20340995426cyclictest0-21swapper01:10:060
20340995425cyclictest0-21swapper03:46:420
20340995425cyclictest0-21swapper03:19:330
20340995425cyclictest0-21swapper02:35:380
20340995425cyclictest0-21swapper00:56:490
20340995424cyclictest0-21swapper01:54:450
20340995424cyclictest0-21swapper01:20:520
20340995423cyclictest0-21swapper04:01:290
20340995423cyclictest0-21swapper01:31:220
20340995332cyclictest0-21swapper03:51:420
20340995326cyclictest0-21swapper02:31:270
20340995326cyclictest0-21swapper01:28:060
20340995324cyclictest0-21swapper02:39:380
20340995227cyclictest0-21swapper04:10:370
20340995224cyclictest0-21swapper02:12:340
20340993710cyclictest13680-21munin-node23:55:090
2034099369cyclictest0-21swapper23:39:370
20340993510cyclictest25897-21munin-node23:00:030
2034099349cyclictest0-21swapper23:33:530
20340993410cyclictest24075-21munin-node22:55:080
2034099339cyclictest0-21swapper00:15:300
2034099339cyclictest0-21swapper00:11:270
2034099329cyclictest0-21swapper00:09:330
20340993221cyclictest15880-21iostat_ios00:00:050
20340993210cyclictest26465-21munin-node00:30:060
20340993210cyclictest10091-21munin-node23:45:040
2034099319cyclictest0-21swapper00:21:190
20340993123cyclictest0-21swapper00:24:590
20340993122cyclictest31310-21wc23:14:480
20340993122cyclictest19422sleep023:21:130
20340993121cyclictest226302sleep022:50:110
20340993121cyclictest20331-21cyclictest00:34:590
20340993121cyclictest12200-21if_eth223:50:070
20340993120cyclictest36582sleep023:25:340
20340993120cyclictest31757-21iostat_ios23:15:070
20340993110cyclictest31887-21latency_hist00:44:430
20340993110cyclictest0-21swapper23:06:020
20340993020cyclictest93632sleep023:41:430
20340993019cyclictest204242sleep022:45:050
20340992313cyclictest20349-21cat22:44:510
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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