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2022-08-20 - 05:32

x86 Intel Celeron M @1500 MHz, Linux 3.2.39-rt59 (Profile)

Latency plot of system in rack #2, slot #6
Data to construct the above plot have been generated using the RT test utility cyclictest.
Command line: cyclictest -l100000000 -m -n -a0 -t1 -p99 -i200 -h400 -q
Total number of samples: 100 million
Resolution of latency scale: normal
Duration: 5 hours, 33 minutes
Compare latency of primary with shadow system
Characteristics of the 100, highest latencies:
System rack2slot6.osadl.org (updated Sat Aug 20, 2022 00:43:23)
Delayed (victim)Switcher (culprit)TimestampCPU
PIDPrioTotal
latency
(µs)
T*(,W**)
latency
(µs)
CmdPIDPrioCmd
311610ksoftirqd/029201-21threads16:49:340
5039995829cyclictest21455-21netstat17:54:240
5039995231cyclictest0-21swapper18:10:580
5039994926cyclictest0-21swapper18:59:310
5039994915cyclictest15355-21kworker/0:016:48:040
5039994828cyclictest0-21swapper17:47:210
5039994823cyclictest0-21swapper16:31:510
5039994810cyclictest0-21swapper18:36:210
503999479cyclictest0-21swapper17:21:360
5039994733cyclictest0-21swapper18:03:020
5039994730cyclictest0-21swapper19:19:340
5039994727cyclictest0-21swapper16:39:100
5039994714cyclictest5213-21kworker/0:116:04:390
5039994714cyclictest15261-21kworker/0:019:06:200
5039994711cyclictest0-21swapper18:44:360
5039994710cyclictest0-21swapper19:26:560
5039994710cyclictest0-21swapper18:52:340
503999469cyclictest0-21swapper18:21:010
5039994626cyclictest0-21swapper19:16:170
5039994616cyclictest9445-21kworker/0:117:27:540
5039994616cyclictest15261-21kworker/0:018:25:420
5039994615cyclictest5213-21kworker/0:116:16:030
5039994613cyclictest5213-21kworker/0:116:03:260
5039994612cyclictest9445-21kworker/0:118:16:590
5039994612cyclictest15355-21kworker/0:017:03:500
5039994610cyclictest0-21swapper19:13:200
5039994610cyclictest0-21swapper17:51:020
5039994610cyclictest0-21swapper17:33:240
5039994610cyclictest0-21swapper16:41:060
503999458cyclictest0-21swapper17:34:180
503999458cyclictest0-21swapper16:20:170
5039994528cyclictest0-21swapper18:07:150
5039994516cyclictest9445-21kworker/0:117:14:200
5039994516cyclictest15355-21kworker/0:016:56:470
5039994516cyclictest15261-21kworker/0:018:40:030
5039994515cyclictest9445-21kworker/0:117:40:590
5039994512cyclictest9445-21kworker/0:117:09:220
5039994511cyclictest0-21swapper17:07:580
5039994510cyclictest0-21swapper18:57:370
503999449cyclictest0-21swapper16:26:290
503999449cyclictest0-21swapper16:10:390
5039994414cyclictest15261-21kworker/0:018:33:440
5039994325cyclictest5037-21cyclictest15:59:150
503999359cyclictest27065-21munin-node14:59:330
5039993512cyclictest0-21swapper15:50:140
5039993511cyclictest0-21swapper14:39:430
5039993412cyclictest9366-21munin-node15:39:360
503999339cyclictest0-21swapper14:44:240
5039993310cyclictest5125-21munin-node13:59:370
503999328cyclictest0-21swapper14:31:000
5039993223cyclictest0-21swapper15:34:330
5039993210cyclictest0-21swapper15:14:400
5039993210cyclictest0-21swapper14:36:420
503999319cyclictest0-21swapper15:32:460
503999319cyclictest0-21swapper14:13:490
503999318cyclictest28889-21munin-node15:04:370
5039993122cyclictest0-21swapper14:05:280
5039993121cyclictest0-21swapper14:49:460
5039993120cyclictest115862sleep014:15:150
5039993110cyclictest25230-21munin-node14:54:330
5039993020cyclictest47382sleep015:24:400
5039993020cyclictest21682sleep015:19:330
5039993020cyclictest122762sleep015:45:450
5039993010cyclictest30741-21munin-node15:09:390
5039993010cyclictest0-21swapper14:24:360
5039992919cyclictest0-21swapper14:19:370
385022813sleep03904-21munin-node13:54:430
*Timer  **Wakeup  (latency=timer+wakeup+contextswitch)

 

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